Reversed phase-locked loop

Abstract

A phase-locked loop (PLL) frequency synthesizer is connected in reverse to a reference signal and a controlled oscillator loop including a low pass filter and a voltage-controlled oscillator (VCO). Rather than receiving a reference signal through a reference oscillator input and a VCO output signal through a VCO input, the PLL frequency synthesizer receives a reference signal through the VCO input and receives the VCO output signal through the reference oscillator input. Additionally, the output of the PLL is taken from the buffered reference output, thereby eliminating the need for an external buffer. Accordingly, the data loaded into the PLL frequency synthesizer accommodates the reversed input scheme by altering the divide ratios and inverting the phase detector output signal. In addition, a selective grounding network is connected to the reference oscillator input of the PLL frequency synthesizer to greatly reduce power consumption of the PLL frequency synthesizer, and as part of the same effort, a voltage switch is utilized to remove power to the VCO.

We claim: 
     
       1. A phase-locked loop circuit comprising: means responsive to a control signal for oscillating to produce a loop signal at a first frequency with a phase controlled by said control signal;   means connected to said oscillating means responsive to said loop signal and a reference signal for generating said control signal and for buffering said loop signal to produce a controlled buffered output signal; and   means for selectively grounding said loop signal to reduce power consumption of said generating buffering means.   
     
     
       2. The circuit of claim 1, wherein said oscillating means includes, at least, means coupled to said generating buffering means for filtering said control signal received from said generating buffering means and   means coupled to said filtering means for controllably oscillating at a frequency determined by a voltage from said filtering means, and     wherein said generating buffering means includes, at least, means for detecting phase differences between said reference signal and said loop signal and   means for buffering said loop signal.     
     
     
       3. The circuit of claim 2, wherein said filtering means includes, at least, a low pass filter, and wherein said controllably oscillating means includes, at least, a voltage-controlled oscillator. 
     
     
       4. The circuit of claim 1, wherein said oscillating means includes, at least, a low pass filter coupled to a voltage-controlled oscillator responsive to the voltage level of said control signal, and wherein said generating buffering means includes, at least, a phase-locked loop frequency synthesizer including, at least, an internal buffer. 
     
     
       5. The circuit of claim 4, wherein said phase-locked loop frequency synthesizer further includes, at least, means for receiving and storing configuration data, and wherein said phase-locked loop frequency synthesizer is further responsive to said configuration data in generating said control signal. 
     
     
       6. The circuit of claim 4, wherein said phase-locked loop frequency synthesizer further includes, at least, means for dividing said loop signal down to a divided loop signal and for dividing said reference down to a divided reference signal, and   means for detecting a phase difference between said divided loop signal and said divided reference signal and for generating said control signal based upon said phase difference.   
     
     
       7. The circuit of claim 6, wherein said phase-locked loop frequency synthesizer further includes means for detecting a phase equivalence between said divided loop signal and said divided reference signal and for generating a lock detect signal. 
     
     
       8. A phase-locked loop circuit for receiving as input a reference signal at a reference frequency over a reference signal line and producing as output a controlled output signal at a controlled output frequency on a controlled output signal line, said circuit comprising: a buffered phase detector device including, at least, a phase detector including, at least, a first phase detector input coupled to the reference signal line,   a second phase detector input coupled to a controlled oscillator output line, and   a phase detector output coupled to a controlled oscillator control line, and     a buffer including, at least, a multi-stage reference divider configured to divide by one,   a buffer input coupled to said second phase detector input, and   a buffer output coupled to the controlled output signal line;       a loop filter including, at least, a loop filter input coupled to said controlled oscillator control line, and   a loop filter output coupled to a loop filter output line; and a controlled oscillator including, at least,   a controlled oscillator input coupled to said loop filter output line, and   a controlled oscillator output coupled to said controlled oscillator output line.     
     
     
       9. The circuit of claim 8, further comprising a phase-locked loop frequency synthesizer including, at least, said buffered phase detector. 
     
     
       10. The circuit of claim 9, wherein said phase-locked loop frequency synthesizer further includes, at least, a loop frequency input interposed between the reference signal line and said first phase detector input, and   a reference oscillator input interposed between said controlled oscillator output line and said second phase detector input.   
     
     
       11. The circuit of claim 9, wherein said phase-locked loop frequency synthesizer further includes, at least, a first counter interposed between said reference signal line and said first phase detector input,   a second counter interposed between said controlled oscillator output line and said second phase detector input, and   counter configuration memory elements.   
     
     
       12. The circuit of claim 11, wherein said phase-locked loop frequency synthesizer further includes, at least, a lock detector coupled to said first counter and said second counter. 
     
     
       13. The circuit of claim 8, wherein said loop filter includes, at least, a low pass filter. 
     
     
       14. The circuit of claim 8, further comprising a selective grounding network coupled to said controlled oscillator output line. 
     
     
       15. A phase-locked loop circuit for receiving as input a reference signal at a reference frequency over a reference signal line and producing as output a controlled output signal at a controlled output frequency on a controlled output signal line, said circuit comprising: a phase-locked loop frequency synthesizer contained in a single integrated circuit including, at least, a reference oscillator input,   a reference buffer coupled to said reference oscillator input and including a multi-stage divider configured to divide by one,   a buffered reference output coupled to said reference buffer and further coupled to the controlled output signal line,   a reference frequency counter coupled to said reference oscillator input,   a reference oscillator interposed between said reference oscillator input and said reference frequency counter,   a loop frequency input coupled to the reference signal line,   a loop frequency counter coupled to said loop frequency input,   an input amplifier interposed between said loop frequency input and said loop frequency counter,   a phase detector coupled to said reference frequency counter and said loop frequency counter, and   a phase detector output coupled to said phase detector; and     a voltage-controlled oscillator loop coupled to said phase-locked loop frequency synthesizer including, at least, a loop filter coupled to said phase detector output of said phase-locked loop frequency synthesizer, and   a voltage-controlled oscillator including, at least, a voltage-controlled oscillator input coupled to said loop filter, and   a voltage-controlled oscillator output coupled to said reference oscillator input of said phase-locked loop frequency synthesizer.       
     
     
       16. The circuit of claim 15, wherein said loop filter includes, at least, a low pass filter. 
     
     
       17. The circuit of claim 15, wherein said phase-locked loop frequency synthesizer further includes, at least, counter configuration memory elements. 
     
     
       18. The circuit of claim 15, wherein said phase-locked loop frequency synthesizer further includes, at least, a lock detector coupled to said reference frequency counter and said loop frequency counter and a lock detector output coupled to said lock detector. 
     
     
       19. The circuit of claim 15, further comprising a selective grounding network coupled to said reference oscillator input. 
     
     
       20. In combination: a frequency source;   a phase-locked loop frequency synthesizer coupled to said frequency source including, at least, a first input,   a buffered output of said first input,   a second input coupled to said frequency source, and   a phase detector output;     a phase-locked loop voltage-controlled oscillator coupled to said phase-locked loop frequency synthesizer including, at least, an input coupled to said phase detector output of said phase-locked loop frequency synthesizer, and   an output coupled to said first input of said phase-locked loop frequency synthesizer; and     a code division multiple access (CDMA) baseband application-specific integrated circuit (ASIC) and a CDMA mobile station modem coupled to said buffered output of said first input.   
     
     
       21. The combination of claim 20, wherein said first input defines a reference oscillator input, wherein said buffered output defines a reference output, and wherein said second input defines a loop frequency input. 
     
     
       22. The combination of claim 20, wherein said frequency source includes, at least, a stable crystal oscillator. 
     
     
       23. The combination of claim 20, wherein said frequency source includes, at least, a voltage-controlled, temperature-compensated crystal oscillator conductively connected to a linearly biased, isolating digital buffer. 
     
     
       24. The combination of claim 20, wherein said phase-locked loop frequency synthesizer further includes, at least, first convening means for converting signals passing through said first input to a first frequency,   second convening means for converting signals passing through said second input to a second frequency, and   means for detecting phase differences between signals from said first convening means and said second converting means and for producing signals on said phase detector output corresponding to the phase differences.   
     
     
       25. The combination of claim 20, further comprising a selective grounding network coupled to said first input of said phase-locked loop frequency synthesizer. 
     
     
       26. The combination of claim 25, wherein said selective grounding network includes, at least, a diode connected in series with a resistor to a selective ground. 
     
     
       27. A method of generating a buffered output signal at a synthesized frequency, said method comprising the steps of: providing a voltage-controlled oscillator loop connected to a phase-locked loop frequency synthesizer with an internal buffer;   generating and supplying to a reference oscillator input on the phase-locked loop frequency synthesizer a loop signal oscillating at a loop frequency;   receiving a reference signal with a reference frequency at a loop signal input on the phase-locked loop frequency synthesizer;   generating and supplying to the voltage-controlled oscillator loop a control signal responsive to said loop signal and said reference signal; and   buffering said loop signal with said internal buffer to output a buffered, output signal from said phase-locked loop frequency synthesizer.   
     
     
       28. The method of claim 27, wherein the step of generating and supplying to the voltage-controlled oscillator loop a control signal responsive to said loop signal and said reference signal includes the steps of: dividing the loop signal down to a divided loop signal;   dividing the reference signal down to a divided reference signal;   detecting a phase difference between the divided loop signal and the divided reference signal; and   generating the control signal based upon the detected phase difference.   
     
     
       29. The method of claim 28, further comprising the step of generating and outputting a lock detect signal upon detecting phase equality between the divided loop signal and the divided reference signal. 
     
     
       30. The method of claim 28, further comprising the step of receiving and storing configuration data at the phase-locked loop frequency synthesizer for controlling the dividing steps. 
     
     
       31. The method of claim 27, further comprising the step of selectively grounding the reference oscillator input and removing power to the voltage-controlled oscillator loop.