Single-port network node transceiver with powered-down protection

Abstract

A single-port network node transceiver that does not draw any substantial current from the network when it is powered-down, enabling it to meet the ISDN powered-down loading specification when built on a CMOS integrated circuit chip. The pull-up transistors of the transmitter output circuit each have means for shorting the well terminal to source terminal connection when the circuit is operating and opening the connection when the power to the transceiver is shut down. The opening of this connection prevents the well-substrate junction of the pull-up transistors from becoming forward biased and drawing current from the network when the power to the transceiver is off and there is voltage present on the network. The transceiver also includes a plurality of ESD overvoltage protection diodes in series between the power supply rail and each input/output terminal. Since multiple diodes are connected in series and their voltage drops are added together, the diodes also do not draw current from the network when the transceiver is powered down.

We claim: 
     
       1. A transmitter output circuit for a single-port communications node transceiver, the circuit comprising: first and second supply voltage terminals;   first and second input terminals;   a reference current input terminal;   a first transistor pair including a first pull-up transistor having a gate terminal connected to the first input terminal and having a well terminal, a source terminal and a drain terminal, the drain terminal of the first pull-up transistor connected to the reference current input terminal, and further including a first pull-down transistor having a source terminal, a drain terminal and a gate terminal, the gate terminal of the first pull-down transistor connected to the second input terminal, the first transistor pair connected between the reference current input terminal and the second supply voltage terminal so that the drain terminal of the first pull-up transistor is connected to the reference current input terminal and the source terminal of the first pull-down transistor is connected to the second supply voltage terminal;   a second transistor pair including a second pull-up transistor having a gate terminal connected to the second input terminal and having a well terminal, a source terminal and a drain terminal, the drain terminal of the second pull-up transistor connected to the reference current input terminal, and further including a second pull-down transistor having a source terminal, a drain terminal and a gate terminal, the gate terminal of the second pull-down transistor connected to the first input terminal, the second transistor pair connected between the reference current input terminal and the second supply voltage terminal so that the drain terminal of the second pull-up transistor is connected to the reference current input terminal and the source terminal of the second pull-down transistor is connected to the second supply voltage terminal;   a pair of output terminals one of the pair of output terminals connected to the source terminal of the first pull-up transistor and the drain terminal of the first pull-down transistor, and another of the pair of output terminals connected to the source terminal of the second pull-up transistor and the drain terminal of the second pull-down transistor; and   means connected between the well terminal and the source terminal for each pull-up transistor, and also connected to the first supply voltage terminal, for shorting the well and source terminals together when voltage is applied to the first supply voltage terminal and disconnecting the well and source terminals when no voltage is applied.   
     
     
       2. The transmitter output circuit of claim 1 wherein the means for shorting the well and source terminals for each pull-up transistor together is a transistor having a gate connected to the first supply voltage terminal and a well terminal connected to the second supply voltage terminal. 
     
     
       3. The transmitter output circuit of claim 2 wherein all the transistors are field effect transistors ("FETs"). 
     
     
       4. The transmitter output circuit of claim 2 wherein all the transistors are normally-off n-channel field effect transistors. 
     
     
       5. The transmitter output circuit according to any of claims 1, 2, 3 or 4 further comprising: a plurality of diodes in series connected between each of the pair of output terminals and the first supply voltage terminal; and   a diode connected between each of the pair of output terminals and the second supply voltage terminal.   
     
     
       6. A communications node transceiver chip including one or more single-port communications node transceivers, each communications node transceiver comprising: first and second supply voltage terminals;   a pair of input/output terminals;   a multiplexer for selecting between transmit mode and receive mode;   logic means coupled to the multiplexer for controlling the multiplexer;   a receiver connected between the multiplexer and the input/output terminals; and   a transmitter connected between the multiplexer and the input/output terminals, the transmitter including a transmitter output circuit comprising: first and second input terminals, each connected to the multiplexer;   a reference current input terminal;   a first transistor pair including a first pull-up transistor having a gate terminal connected to the first input terminal and having a well terminal, a source terminal and a drain terminal, the drain terminal of the first pull-up transistor connected to the reference current input terminal, and further including a first pull-down transistor having a source terminal, a drain terminal and a gate terminal, the gate terminal of the first pull-down transistor connected to the second input terminal, the first transistor pair connected between the reference current input terminal and the second supply voltage terminal so that the drain terminal of the first pull-up transistor is connected to the reference current input terminal and the source terminal of the first pull-down transistor is connected to the second supply voltage terminal, and the source terminal of the first pull-up transistor and the drain terminal of the first pull-down transistor are connected to one of the pair input/output terminals;   a second transistor pair including a second pull-up transistor having a gate terminal connected to the second input terminal and having a well terminal, a source terminal and a drain terminal, the drain terminal of the second pull-up transistor connected to the reference current input terminal, and further including a second pull-down transistor having a source terminal, a drain terminal and a gate terminal, the gate terminal of the second pull-down transistor connected to the first input terminal, the second transistor pair connected between the reference current input terminal and the second supply voltage terminal so that the drain terminal of the second pull-up transistor is connected to the reference current input terminal and the source terminal of the second pull-down transistor is connected to the second supply voltage terminal, and the source terminal of the second pull-put transistor and the drain terminal of the second pull-down transistor are connected to another of the pair input/output terminals; and   means connected between the well terminal and the source terminal for each pull-up transistor, and also connected to the first supply voltage terminal for shorting the well and source terminals together when voltage is applied to the first supply voltage terminal and disconnecting the well and source terminals when the voltage is not applied.     
     
     
       7. The communications node transceiver chip of claim 6 wherein the means for shorting the well and source terminals for each pull-up transistor together is a transistor having a gate connected to the first supply voltage terminal and a well terminal connected to the second supply voltage terminal. 
     
     
       8. The communications node transceiver chip of claim 7 wherein all the transistors of the transmitter output circuit are field effect transistors ("FETs"). 
     
     
       9. The communications node transceiver chip of claim 7 wherein all the transistors of the transmitter output circuit are normally off n-channel field effect transistors. 
     
     
       10. The communications node transceiver chip according to any of claims 6, 7, 8 or 9 wherein each single-port node transceiver includes an overvoltage protection circuit comprising: a plurality of diodes in series connected between each of the pair of input/output terminals and the first supply voltage terminal; and   a diode connected between each of the pair of input/output terminals and the second supply voltage terminal.   
     
     
       11. An adapter card for use within a computer system, the adapter card including: one or more communications node transceiver chips mounted on the adapter card, each transceiver chip having one or more pairs of input/output terminals and first and second supply voltage terminals, one or more of the communication node transceiver chips including one or more transmitter output circuits, each transmitter output circuit comprising:   first and second input terminals;   a reference current input terminal;   a first transistor pair including a first pull-up transistor having a gate terminal connected to the first input terminal and having a well terminal, a source terminal and a drain terminal, the drain terminal of the first pull-up transistor connected to the reference current input terminal, and further including a first pull-down transistor having a source terminal, a drain terminal and a gate terminal, the gate terminal of the first pull-down transistor connected to the second input terminal, the first transistor pair connected between the reference current input terminal and the second supply voltage terminal so that the drain terminal of the first pull-up transistor is connected to the reference current input terminal and the source terminal of the first pull-down transistor is connected to the second supply voltage terminal, and the source terminal of the first pull-up transistor and the drain terminal of the first pull-down transistor are connected to one of a given pair of input/output terminals;   a second transistor pair including a second pull-up transistor having a gate terminal connected to the second input terminal and having a well terminal, a source terminal and a drain terminal, the drain terminal of the second pull-up transistor connected to the reference current input terminal, and further including a second pull-down transistor having a source terminal, a drain terminal and a gate terminal, the gate terminal of the second pull-down transistor connected to the first input terminal, the second transistor pair connected between the reference current input terminal and the second supply voltage terminal so that the drain terminal of the second pull-up transistor is connected to the reference current input terminal and the source terminal of the second pull-down transistor is connected to the second supply voltage terminal, and the source terminal of the second pull-up transistor and the drain terminal of the second pull-down transistor are connected to another of the given pair of input/output terminals; and   means connected between the well terminal and the source terminal for each pull-up transistor, and also connected to the first supply voltage terminal for shorting the well and source terminals together when voltage is applied to the first supply voltage terminal and disconnecting the well and source terminals when the voltage is not applied.