Non-volatile semiconductor memory device and a method of using the same

Abstract

An electrically alterable non-volatile semiconductor memory. The memory cells are formed in a matrix of columns and rows. A row decoder and column decoder are provided to select one of the row lines and column lines. Mode selection means are provided for selecting a writing mode, a first erasing mode for erasing a row of memory cells, a second erasing mode for erasing a selected memory cell on a bit basis, and a reading mode for reading the contents of each memory cell. The individual erasing modes reduce the overall power consumption of the device, while permitting block erasing as well as individual cell erasing.

I claim: 
     
       1. An electrically alterable non-volatile semiconductor memory device comprising: a plurality of memory cells formed on a semiconductor substrate and arranged in a matrix of columns and rows, each memory cell having a control gate, a floating gate, a drain and a source;   a plurality of row lines each connected to the control gates of said memory cells arranged in one row;   a plurality of column lines each connected to the drains of said memory cells arranged in one column;   one source line connected to the sources of said plurality of memory cells;   a row decoder for selecting one of said plurality of row lines;   a column decoder for selecting one of said plurality of column lines;   an input terminal for receiving data which is to be written in a selected memory cell;   mode selection means for selecting one of four modes, including a writing mode for setting a selected one of said plurality of memory cells in a written state in accordance with said received data, a first erasing mode for setting a memory cell group arranged in one row including said selected memory cell in an unwritten state, a second erasing mode for setting only the selected memory cell in the unwritten state, and a reading mode for detecting whether said selected memory cell is in said written state or said unwritten state; and   voltage applying means for applying one set of voltages, selected from first, second, third and fourth predetermined sets of voltages, in accordance with the mode selected by said mode selection means to a row line selected by said row decoder, non-selected row lines, a column line selected by said column decoder, non-selected column lines, said source line and said substrate, respectively;   said voltage applying means including voltage selection means for applying a voltage having the same level to said selected column line and said non-selected column lines when said first erasing mode is selected and for applying a first voltage to said selected column line and applying a second voltage higher than said first voltage to said a source line when said second erasing mode is selected.   
     
     
       2. A non-volatile semiconductor memory device according to claim 1, wherein said first voltage is at a ground potential and said second voltage is at a potential higher than the ground potential. 
     
     
       3. A non-volatile semiconductor memory device according to claim 1, wherein said voltage selection means includes means for causing said column decoder not to select less than all of said plurality of column lines in said first erasing mode and to select only a column line connected to said selected memory cell in said second erasing mode. 
     
     
       4. A non-volatile semiconductor memory device according to claim 3, wherein said voltage selection means further includes means for applying to said plurality of column lines a voltage having the same level as that of the voltage applied to said substrate in said first erasing mode. 
     
     
       5. A method of using an electrically alterable non-volatile semiconductor memory device including a plurality of memory cells formed on a semiconductor substrate and arranged in a matrix of columns and rows and each having a control gate, a floating gate, a drain and a source, a plurality of row lines each connected to the control gates of said memory cells arranged in one row, a plurality of column lines each connected to the drain of said memory cells arranged in one column, one source line connected to the sources of said plurality of memory cells, a row decoder for selecting one of said plurality of row lines, a column decoder for selecting one of said plurality of column lines, an input terminal for receiving data which is to be written in a selected memory cell, and mode selection means for selecting one of four modes, including a writing mode for setting a selected one of said plurality of memory cells in a written state in accordance with said received data, a first erasing mode for setting a memory cell group arranged in one row including said selected memory cell in an unwritten state, a second erasing mode for setting only said selected memory cell in the unwritten state, and a reading mode for detecting whether said selected memory cell is in said written state or said unwritten state, said method comprising the steps of: applying a voltage having substantially the same level as a voltage applied to said substrate to all of said plurality of column lines and injecting electrons by FN injection from said substrate to said floating gate of each of the memory cells connected to one row line selected by said row decoder thereby setting said memory cells in said unwritten state when said first erasing mode is selected;   setting one column line selected by said column decoder in a ground potential and applying a voltage higher than the ground voltage to said source line to inject hot electrons in said floating gate of said selected memory cell thereby setting said selected memory cell in said unwritten state when said second erasing mode is selected; and   applying a voltage having substantially the same level as the voltage applied to said source line to the column lines other than one column line selected by said column decoder to prevent hot electrons from being injected in the floating gates of those memory cells connected to said selected row line other than said selected one.   
     
     
       6. A method according to claim 5, further comprising: a step of applying a voltage having substantially the same level as a voltage applied to said substrate to said source line when said first erasing mode is selected; and   a step of setting said substrate to the ground potential when said second erasing mode is selected.   
     
     
       7. A method according to claim 5, further comprising a step of setting one column line selected by said column decoder to the grounds potential or a voltage higher than the ground potential in accordance with a level of a signal applied to said input terminal when said second erasing mode is selected and preventing hot electrons from being injected in the floating gate of said selected memory cell when the voltage higher than the ground potential is applied.