Single-etch stop process for the manufacture of silicon-on-insulator substrates

Abstract

A single-etch stop process for the manufacture of silicon-on-insulator substrates. The process includes forming a silicon-on-insulator bonded substrate comprising a handle wafer, a device wafer, a device layer having a thickness of between about 0.5 and 50 micrometers, and an oxide layer with the device layer being between the device wafer and the oxide layer and the oxide layer being between the device layer and the handle wafer, the device wafer having a boron concentration of at least about 1×10 18 boron atoms/cm 3 and a resistivity of about 0.01 to about 0.02 ohm-cm. A portion of the device wafer is mechanically removed from the silicon-on-insulator bonded substrate wherein the device wafer has a total thickness variation across the surface of the wafer of less than about 2 micrometers and a defect-free surface after the mechanical removal step. The defect-free surface of the device wafer is thereafter etched away to expose the device layer, and the exposed device layer is polished to produce a silicon-on-insulator substrate having a device layer the total thickness variation of which does not exceed 10% of the maximum thickness of the device layer.

What is claimed is: 
     
       1. A single-etch stop process for the manufacture of silicon-on-insulator substrates comprising forming a silicon-on-insulator bonded substrate comprising a handle wafer, a device wafer, a device layer having a thickness of between about 0.5 and 50 micrometers, and an oxide layer with the device layer being between the device wafer and the oxide layer and the oxide layer being between the device layer and the handle wafer, the device wafer having a boron concentration of at least about 1×10 18  boron atoms/cm 3  and a resistivity of about 0.01 to about 0.02 ohm-cm,   removing a portion of the device wafer from the silicon-on-insulator bonded substrate, the device wafer having a total thickness variation across the surface of the wafer of less than about 2 micrometers and a defect-free surface after the removal step,   etching away the defect-free surface of the device wafer to expose the device layer, and   polishing the exposed device layer to produce a silicon-on-insulator substrate having a device layer the total thickness variation of which does not exceed 10% of the maximum thickness of the device layer.   
     
     
       2. A process as set forth in claim 1 wherein the step of removing a portion of the device wafer comprises a two-stage process in which a coarse material removal stage is followed by a smooth grinding stage. 
     
     
       3. A process as set forth in claim 2 wherein the coarse material removing stage comprises chemically etching or grinding. 
     
     
       4. A process as set forth in claim 2 wherein the step of removing a portion of the device wafer additionally comprises polishing the surface of the device wafer after the smooth grinding stage. 
     
     
       5. A process as set forth in claim 1 wherein the step of etching away the defect-free surface of the device wafer comprises immersing the silicon-on-insulator bonded substrate in a bath containing hydrofluoric acid, nitric acid and acetic acid and reconditioning the bath by adding peroxide, ozone or other oxidant to the bath. 
     
     
       6. A process as set forth in claim 1 wherein the step of etching away the defect-free surface of the device wafer comprises immersing the silicon-on-insulator bonded substrate in a bath containing hydrofluoric acid, nitric acid and acetic acid and, after the etch rate begins to diminish, withdrawing the silicon-on-insulator bonded substrate from the bath, reactivating the device wafer surface, and reimmersing the silicon-on-insulator bonded substrate in the bath containing hydrofluoric acid, nitric acid and acetic acid. 
     
     
       7. A process as set forth in claim 6 wherein the device wafer surface is reactivated by being exposed to air or by being immersed in water. 
     
     
       8. A process as set forth in claim 6 wherein the steps of reactivating the device wafer surface and reimmersing the silicon-on-insulator bonded substrate in the bath containing hydrofluoric acid, nitric acid and acetic acid are repeated at least twice. 
     
     
       9. A process as set forth in claim 8 wherein the device wafer surface is reactivated by being exposed to air or by being immersed in water. 
     
     
       10. A process as set forth in claim 8 wherein the surface is reactivated by immersing the surface in water and the water contains ozone. 
     
     
       11. A process as set forth in claim 1 wherein the exposed device layer is polished using an ammonia stabilized colloidal silica slurry. 
     
     
       12. A process as set forth in claim 1 wherein no more than about 200 nm of silicon are removed when the exposed device layer is polished. 
     
     
       13. A process as set forth in claim 1 wherein the thickness of the device wafer after the step of mechanically removing a portion of the device wafer from the silicon-on-insulator bonded substrate is between about 10 and about 30 micrometers. 
     
     
       14. A process as set forth in claim 1 wherein the periphery of the bonded silicon-on-insulator bonded substrate is abraded by grinding. 
     
     
       15. A process as set forth in claim 1 wherein the silicon-on-insulator bonded substrate is subjected to a high temperature annealing step to increase the bonding strength after the device wafer is etched away to expose the device layer. 
     
     
       16. A single-etch stop process for the manufacture of silicon-on-insulator substrates comprising forming a silicon-on-insulator bonded substrate comprising a handle wafer, a device wafer, a device layer having a thickness of between about 0.5 and 50 micrometers, and an oxide layer with the device layer being between the device wafer and the oxide layer and the oxide layer being between the device layer and the handle wafer, the device wafer having a boron concentration of at least about 1×10 18  boron atoms/cm 3  and a resistivity of about 0.01 to about 0.02 obm-cm,   grinding away a portion of the device wafer from the silicon-on-insulator bonded substrate and polishing the ground surface of the device wafer, the device wafer having a thickness of between about 10 and about 30 micrometers, a total thickness variation across the surface of the wafer of less than about 2 micrometers, and a defect-free surface after the ground surface is polished,   etching away the defect-free surface of the device wafer to expose the device layer, and   polishing the exposed device layer using an ammonia stabilized colloidal silica slurry to produce a silicon-on-insulator substrate having a device layer the total thickness variation of which does not exceed 10% of the maximum thickness of the device layer, the amount of silicon being removed from the exposed device layer during the polishing step being no more than about 200 nm of the thickness of the exposed device layer.   
     
     
       17. A process as set forth in claim 16 wherein the silicon-on-insulator bonded substrate is subjected to a high temperature annealing step to increase the bonding strength after the device wafer is etched away to expose the device layer. 
     
     
       18. A process as set forth in claim 16 wherein the step of etching away the defect-free surface of the device wafer comprises immersing the silicon-on-insulator bonded substrate in a bath containing hydrofluoric acid, nitric acid and acetic acid and, after the etch rate begins to diminish, withdrawing the silicon-on-insulator bonded substrate from the bath, reactivating the device wafer surface, and reimmersing the silicon-on-insulator bonded substrate in the bath containing hydrofluoric acid, nitric acid and acetic acid. 
     
     
       19. A process as set forth in claim 18 wherein the device wafer surface is reactivated by being exposed to air or by being immersed in water. 
     
     
       20. A process as set forth in claim 18 wherein the steps of reactivating the device wafer surface and reimmersing the silicon-on-insulator bonded substrate in the bath containing hydrofluoric acid, nitric acid and acetic acid are repeated at least twice. 
     
     
       21. A process for etching silicon from the surface of a substrate in an etchant comprising hydrofluoric acid, nitric acid and acetic acid, the process comprising contacting the surface with the etchant and, after the etch rate begins to diminish, reactivating the surface by exposing the surface to air or by immersing the surface in water and thereafter again contacting the surface with the etchant. 
     
     
       22. A process as set forth in claim 21 wherein the surface is reactivated by immersing the surface in water and the water contains oxygen or ozone.