Method of fabricating an electrically alterable resistive component on an insulating layer

Abstract

A memory cell includes a pair of spaced apart conductors on an insulating layer, and a novel electrically alterable resistive component between the conductors. This resistive component consist essentially of silicon, having a crystalline grain size which is smaller than polycrystalline with dopant atoms that are interstitial in the silicon. Process temperatures are limited such that the dopant atoms remain interstitial and do not become substitutional.

What is claimed is: 
     
       1. A process for fabricating an electrically alterable resistive component in an integrated circuit which includes a semiconductor substrate having a major surface and an insulating layer over said surface; said process including the steps of: forming a bottom electrical lead on said insulating layer;   depositing and patterning a layer of electrically alterable material such that the patterned electrically alterable material overlies and is coupled to said bottom lead;   forming a top electrical lead which extends over and is there coupled to said electrically alterable material;   limiting said electrically alterable material to consist essentially of silicon having dopant atoms which are at interstitial locations in said silicon;   confining said electrically alterable material, from its deposition to the end of said process, to temperatures of less than 600° C.; and,   applying a threshold voltage across said top and bottom electrical leads with a magnitude that causes said silicon to switch irreversibly from an initial high resistance to a greatly reduced resistance.   
     
     
       2. A process according to claim 1, wherein said dopant atoms include arsenic. 
     
     
       3. A process according to claim 1, wherein said dopant atoms include phosphorous. 
     
     
       4. A process according to claim 1, wherein said dopant atoms include antimony. 
     
     
       5. A process according to claim 1 wherein said initial high resistance is at least one thousand times larger than said greatly reduced resistance. 
     
     
       6. A process for fabricating an electrically alterable resistive consonant in an integrated circuit which includes substrate having a major surface and a patterned insulating layer on said surface, said process including the steps of: forming a bottom electrical lead on said insulating layer;   depositing and patterning a layer of electrically alterable material such that the patterned electrically alterable material overlies and is coupled to said bottom lead;   forming a top electrical lead which extends over and is there coupled to said electrically alterable material;   limiting said electrically alterable material to consist essentially of amorphous silicon having dopant atoms which are at interstitial locations in said silicon; and,   confining said electrically alterable material from its deposition to the end of said process to temperatures which prevent column shaped crystalline grains from growing in said silicon from one lead to the other.