Circuit for delaying data latching from a precharged bus and method

Abstract

An latch circuit includes an input line receiving electrical signals from a bus, a latch for conducting electrical signals from the precharged bus to a receiving circuit, and a structure for enabling the latch only when data is driven onto the bus.

What is claimed is: 
     
       1. In a system in which data may be driven on a bus during a data-drive phase, a circuit for passing data from the bus to a receiving circuit, the circuit comprising: an input line for receiving data from the bus;   a transistor having an input and an output, the input connected to the input line, and the output connected to the receiving circuit;   an enabling means coupled to said bus and said transistor for detecting valid data of a predetermined level and for turning on the transistor when valid data is present on the bus during said data-drive phase, said enabling means comprising:   a delay means, comprising at least one inverter having an input connected to a data-valid signal, for receiving and delaying said data-valid signal; and   a control means, having a first input connected to an output of said inverter and a second input connected to said data-clock signal, for receiving said data-clock signal and said delayed data-valid signal and for producing a enable signal which is connected to a gate of said transistor.   
     
     
       2. A method of preventing the receipt by a receiving circuit of precharge values from a precharged bus, the precharged bus being driven to a precharge value during, precharge phases and being capable of being driven with data during data-drive phases, the method comprising the steps of: providing a data-clock signal that indicates the timing of data-drive phases and precharge phases;   providing an indicator signal that indicates valid data is being driven on said precharged bus;   receiving said data-clock signal;   receiving said indicator signal;   delaying said indicator signal;   combining the data-clock signal and the delayed indicator signal into an enable signal, the enable signal being asserted when valid data is Being driven on the precharged bus during a data-drive phase;   enabling the conduction of electrical signals from the precharged bus to the receiving circuit only when the enable signal is asserted.   
     
     
       3. The method as recited in claim 2 wherein the step of delaying comprises the step of delaying the indicator signal through at least one inverter.