Semiconductor memory system having sense amplifier being activated late during clock cycle

Abstract

A memory system is provided wherein array signals begin at the start of a first phase of a system clock and a sense amplifier set signal is developed during a second phase of the system clock which includes an array of memory cells including word lines and bit lines, word drivers connected to the word lines, a word address decoder enabled by the first phase of the clock system and coupled to the word drivers, a bit switch coupling a bit line to a sense amplifier, a system clock inverting circuit, a timing circuit having a first input connected to a late select signal, a second input connected to the inverting circuit and an output connected to the bit switch and a delay circuit having an input coupled to the inverting circuit and an output connected to the sense amplifier.

What is claimed is: 
     
       1. A memory system comprising an array having a plurality of memory cells, each of said memory cells having a cell voltage signal having one of a plurality of predetermined voltage magnitudes stored therein, a sense amplifier,   a system clock having a voltage with a first phase of a given voltage magnitude and a subsequent second phase of a voltage magnitude significantly different from the given voltage magnitude,   means responsive to the first phase of the voltage of said system clock for applying the cell voltage signal from a selected one of said memory cells to an input of said sense amplifier, and   means responsive to the second phase of the voltage of said system clock and to a given voltage signal of a given voltage magnitude having its onset delayed with respect to the onset of the second phase of the voltage of said system clock for enabling said sense amplifier at a time subsequent to the arrival of the cell voltage signal at the input of said sense amplifier.   
     
     
       2. A memory system comprising an array having a plurality of memory cells, each of said memory cells having a cell voltage signal having one of a plurality of predetermined voltage magnitudes stored therein,   a sense amplifier having an input,   a bit switch having an input and an output disposed between said array and the input of said sense amplifier,   a system clock having a voltage with a first phase of a given voltage magnitude and a second phase of a voltage magnitude significantly different from the given voltage magnitude,   first means responsive to the first phase of the voltage of said system clock for applying the cell voltage signal from a selected one of said memory cells to the input of said bit switch, and   second means including a timing circuit responsive to the second phase of the voltage of said system clock and to a late select signal for activating said bit switch at a time subsequent to the arrival of the cell voltage signal at the input of said bit switch and including a delay circuit responsive to the second phase of the voltage of said system clock for enabling said sense amplifier at a time subsequent to the arrival of the late select signal.   
     
     
       3. A memory system as set forth in claim 2 wherein said first means includes a word address decoder and said second means includes an inverting circuit connected to said timing circuit and to said delay circuit. 
     
     
       4. A memory system as set forth in claim 3 wherein said delay circuit of said second means includes an input coupled to an output of said inverting circuit and an output connected to said sense amplifier. 
     
     
       5. A memory system as set forth in claim 4 wherein said sense amplifier includes a latch and a pull-down transistor serially connected with said latch, the out of said delay circuit being connected to a control electrode of said pull-down transistor. 
     
     
       6. A memory system comprising an array having a plurality of word lines, a plurality of pairs of bit lines arranged orthogonal to said plurality of word lines and a plurality of memory cells disposed at the intersections of said plurality of word lines and said plurality of pairs of bit lines, each of said memory cells having a voltage signal of one of a plurality of predetermined voltage magnitudes stored therein,   a differential sense amplifier having first and second inputs,   a system clock having a voltage with a first phase of a given voltage magnitude and a subsequent second phase of a voltage magnitude significantly different from the given voltage magnitude,   first means responsive to the first phase of the voltage of said system clock for applying the voltage signals from first and second memory cells of said plurality of memory cells to first and second pairs of bit lines of said plurality of pairs of bit lines,   first and second bit switches, each having first and second inputs and first and second outputs connected to the first and second inputs, respectively, of said differential sense amplifier, the first and second inputs of said first bit switch being coupled to said first pair of bit lines and the first and second inputs of said second bit switch being coupled to said second pair of bit lines, and   second means responsive to said second phase of the voltage of said system clock for activating said differential sense amplifier at a given instant of time, said second means including a timing circuit responsive to said second phase of the voltage of said system clock and to a given voltage signal delayed with respect to the onset of said second phase of the voltage of said system clock for activating one of said first and second bit switches at an instant of time prior to said given instant of time.   
     
     
       7. A memory system comprising an array having a plurality of memory cells, each of said memory cells having a voltage signal having one of a plurality of predetermined voltages stored therein,   a sense amplifier,   a system clock having a voltage with a first phase of a given voltage magnitude and a second phase of a voltage magnitude significantly different from the given voltage magnitude,   first means including a word address decoder responsive to the first phase of the voltage of said system clock for applying the voltage signal from a selected one of said memory cells to an input of said sense amplifier, and   second means including an inverting circuit and a bit switch responsive to the second phase of the voltage of said system clock for enabling said sense amplifier at a time subsequent to the arrival of the voltage signal at the input of said sense amplifier, said inverting circuit being serially connected with a delay means and said bit switch being disposed between said array and said sense amplifier, said second means further including a timing circuit having a first input connected to an output of said inverting circuit and a second input connected to a late select signal and an output connected to said bit switch.   
     
     
       8. A memory system as set forth in claim 7 wherein said timing circuit is an AND circuit. 
     
     
       9. A memory system as set forth in claim 7 wherein said bit switch includes passgates and a first inverter connected serially with a second inverter with the output of said timing circuit connected to said passgates through said first and second inverters. 
     
     
       10. A memory system comprising an array having a plurality of memory cells, each of said memory cells having a voltage signal having one of a plurality of predetermined voltage magnitudes stored therein, and further including a plurality of word lines and a plurality of bit lines orthogonally arranged with respect to said plurality of word lines,   a sense amplifier having an input,   a system clock having a voltage with a first phase of a given voltage magnitude and a second phase of a voltage magnitude significantly different from the given voltage magnitude,   means including a word address decoder and a plurality of word drivers responsive to the first phase of the voltage of said system clock for applying the voltage signal from a selected one of said memory cells to the input of said sense amplifier, said plurality of word drivers having inputs coupled to said word address decoder and outputs connected to the word lines of said array, and   means including a bit switch, an inverter, timing means and delay means responsive to the second phase of the voltage of said system clock for enabling said sense amplifier at a time subsequent to the arrival of the voltage signal of predetermined magnitude corresponding to the voltage signal at the input of said sense amplifier, said bit switch being disposed between one of said plurality of bit lines and said sense amplifier, said inverter having an output, said timing means having a late select signal applied to a first input thereof and an output connected to said bit switch and said delay means having an output connected to said sense amplifier, the output of said inverter being coupled to a second input of said timing means and to an input of said delay means.   
     
     
       11. A memory system as set forth in claim 10 wherein said delay means includes a delay circuit having an input an output, said first AND circuit having a first input and an output, said first input of said first AND circuit being connected to the output of said inverter and the output of said first AND circuit being connected to the input of said delay circuit, a second input of said first AND circuit being connected to a reference potential and the output of said delay circuit being connected to said sense amplifier, and said timing means being a second AND circuit. 
     
     
       12. A memory system as set forth in claim 10 wherein said plurality of bit lines includes a plurality of pairs of bit lines and said sense amplifier is a differential sense amplifier. 
     
     
       13. A memory system comprising an array having a plurality of word lines, a plurality of pairs of bit lines arranged orthogonal to said plurality of word lines and a plurality of memory cells disposed at the intersections of said plurality of word lines and said plurality of pairs of bit lines, each of said memory cells having a voltage signal of one of a plurality of predetermined voltage magnitudes stored therein,   a differential sense amplifier having first and second inputs,   a system clock having a voltage with a first phase of a given voltage magnitude and a second phase of a voltage magnitude significantly different from the given voltage magnitude,   means responsive to the first phase of the voltage of said system clock for applying the voltage signals from first and second memory cells of said plurality of memory cells to first and second pairs of bit lines of said plurality of pairs of bit lines,   first and second bit switches, each having first and second inputs and first and second outputs connected to the first and second inputs, respectively, of said differential sense amplifier, the first and second inputs of said first bit switch being coupled to said first pair of bit lines and the first and second inputs of said second bit switch being coupled to said second pair of bit lines, and   means including an inverter, first timing means, second timing means and delay means responsive to said second phase of the voltage of said system clock for activating one of said first and second bit switches at a first instant of time and for activating said differential sense amplifier at a second instant of time subsequent to said first instant of time, said inverter having an input coupled to said system clock and an output, said first timing means having a first late select signal applied to a first input thereof, a second input thereof being coupled to the output of said inverter and an output thereof being coupled to said first bit switch, said second timing means having a second late select signal applied to a first input thereof, a second input thereof being coupled to the output of said inverter and an output thereof being coupled to said second bit switch, and said delay means having an input coupled to the output of said inverter and an output coupled to said sense amplifier.   
     
     
       14. A memory system as set forth in claim 13 wherein said first timing means includes a first AND circuit, said second timing means includes a second AND circuit and said delay means includes a third AND circuit having a first input coupled to the output of said inverter and a delay circuit having an input coupled to an output of said third AND circuit and an output coupled to said differential sense amplifier, a second input of said third AND circuit being connected to a constant high voltage.