Test device and method for signalling metal failure of semiconductor wafer

Abstract

Method and test structures for accurately flagging metal failure on a semiconductor wafer include a monitor structure and a control structure, each of which has a plurality of metal segments. At least one metal segment of the monitor structure has a length prone to failure, while the length of the metal segments in the control structure are such that the control structure is resistant to metal failure. The monitor and control structures are predesigned to have equal resistance when there is no metal failure and a measurable resistance difference upon metal failure in that segment of the monitor structure prone to failure. Upon detecting metal failure in the test device, the wafer is flagged as potentially having metal failure in active circuitry interconnect wiring.

I claim: 
     
       1. A test device for signalling possible metal failure of a semiconductor wafer, said test device comprising: a metal monitor structure prone to metal failure;   a metal control structure resistant to metal failure such that said metal control structure is less prone to metal failure than said metal monitor structure; and    wherein said metal monitor structure and said metal control structure have substantially identical resistances without metal failure of said metal monitor structure and a resistance difference upon metal failure of said metal monitor structure, said resistance difference signalling possible metal failure of said semiconductor wafer.   
     
     
       2. The test device of claim 1, wherein said test device is disposed at an inactive region of said semiconductor wafer. 
     
     
       3. The test device of claim 2, wherein said semiconductor wafer contains multiple integrated circuits and wherein said test device is disposed in a kerf region of said semiconductor wafer. 
     
     
       4. The test device of claim 1, wherein said metal monitor structure is disposed adjacent to said metal control structure on said semiconductor wafer. 
     
     
       5. The test device of claim 4, wherein said metal monitor structure and said metal control structure are electrically series connected. 
     
     
       6. The test device of claim 4, wherein said metal monitor structure and metal control structure are disposed in parallel on said semiconductor wafer. 
     
     
       7. The test device of claim 1, wherein metal failure of said metal monitor structure produces an increase in resistance in said metal monitor structure, and wherein contact pads are included in said metal monitor structure and said metal control structure for facilitating electrical determination of the resistance of said metal monitor structure and the resistance of said metal control structure. 
     
     
       8. The test device of claim 1, wherein said metal monitor structure comprises a layered thin film composition including a layer of a refractory material. 
     
     
       9. The test device of claim 8, wherein said layered thin film composition further includes an aluminum layer, and wherein said metal monitor structure is prone to metal failure in said aluminum layer. 
     
     
       10. A test device for signalling possible metal failure of a semiconductor wafer, said test device comprising: a monitor structure having a first plurality of metal segments electrically connected together, at least one metal segment of said first plurality of metal segments being prone to metal failure;   a control structure having a second plurality of metal segments electrically connected together such that no metal segment of said second plurality of metal segments is prone to metal failure and such that said control structure is less prone to metal failure than said metal monitor structure; and    wherein said monitor structure and said control structure have substantially identical resistances without metal failure of said at least one metal segment prone to metal failure, and a resistance difference upon metal failure of said at least one metal segment prone to metal failure, said resistance difference signalling possible metal failure of said semiconductor wafer.   
     
     
       11. The test device of claim 10, wherein said first plurality of metal segments of said monitor structure comprises X metal segments and said second plurality of metal segments of said control structure comprises Y metal segments, and wherein X=Y. 
     
     
       12. The test device of claim 11, wherein said monitor structure has a length L1 and said control structure has a length L2, and wherein length L1=length L2. 
     
     
       13. The test device of claim 12, wherein said monitor structure and said control structure are disposed in close proximity on said semiconductor wafer. 
     
     
       14. The test device of claim 13, wherein said monitor structure and said control structure are disposed in parallel on said semiconductor wafer. 
     
     
       15. The test device of claim 13, wherein said monitor structure and said control structure are electrically series connected. 
     
     
       16. The test device of claim 10, wherein said monitor structure and said control structure each resides on at least two metallization levels of said semiconductor wafer, and wherein each metal segment of said first plurality of metal segments has at least one adjacent metal segment of said first plurality of metal segments disposed on a different metallization level of said at least two metallization levels, and wherein each metal segment of said second plurality of metal segments has at least one adjacent metal segment of said second plurality of metal segments disposed on a different metallization level of said least two metallization levels. 
     
     
       17. The test device of claim 16, wherein for each of said monitor structure and said control structure said at least two metallization levels comprise a first metallization level M1 and a second metallization level M2 disposed on said semiconductor wafer, and wherein said at least one metal segment prone to metal failure of said first plurality of metal segments resides in said first metallization level M1. 
     
     
       18. The test device of claim 10, wherein said monitor structure and said control structure each resides on a first metallization level M1 and a second metallization level M2 on said semiconductor wafer, and wherein a total length of metal segments of said first plurality of metal segments residing on said first metallization level M1 equals a total length of metal segments of said second plurality of metal segments residing on said first metallization level M1, and wherein a total length of segments of said first plurality of metal segments residing on said second metallization level M2 equals a total length of metal segments of said second plurality of metal segments residing on said second metallization level M2. 
     
     
       19. The test device of claim 10, wherein all metal segments of said first plurality of metal segments and said second plurality of metal segments have an identical predefined metal composition. 
     
     
       20. The test device of claim 19, wherein said identical predefined metal composition includes an aluminum layer, and wherein said at least one metal segment of said first plurality of metal segments prone to metal failure is prone to failure in said aluminum layer. 
     
     
       21. The test device of claim 20, wherein said aluminum layer of each metal segment is physically isolated from the aluminum layer of each adjacent metal segment of said first plurality of metal segments and of said second plurality of metal segments. 
     
     
       22. The test device of claim 21, wherein the aluminum layer of each metal segment of said first plurality of metal segments is electrically connected to the aluminum layer of each adjacent metal segment of said first plurality of metal segments via refractory material and wherein the aluminum layer of each metal segment of said second plurality of metal segments is electrically connected to the aluminum layer of each adjacent metal segment of said second plurality of metal segments via said refractory material. 
     
     
       23. The test device of claim 22, wherein said refractory material comprises either a layer of titanium or a layer of tungsten. 
     
     
       24. The test device of claim 22, wherein said refractory material comprises an interconnecting metal stud of titanium or tungsten. 
     
     
       25. The test device of claim 16, wherein each metal segment of said first plurality of metal segments resides on a single metallization level of said at least two metallization levels on said semiconductor wafer, and wherein each metal segment of said second plurality of metal segments resides on a single metallization level of said at least two metallization levels on said semiconductor wafer. 
     
     
       26. The test device claims 16, wherein said at least one segment of said first plurality of metal segments prone to metal failure comprises a first metal segment on a first metallization level of said at least two metallization levels and a second metal segment on a second metallization level of said at least two metallization levels. 
     
     
       27. The test device of claim 10, wherein said monitor structure and said control structure are disposed at an inactive region of said semiconductor wafer. 
     
     
       28. The test device of claim 27, wherein said semiconductor wafer includes multiple integrated circuits and wherein said monitor structure and said control structure are disposed in a kerf region of said semiconductor wafer. 
     
     
       29. A metal test structure for indicating possible metal failure of a semiconductor wafer, said metal test structure comprising: a plurality of test devices disposed in an inactive region of said semiconductor wafer, each test device of said plurality of test devices comprising: a metal monitor structure prone to metal failure;   a metal control structure resistant to metal failure such that said metal control structure is less prone to metal failure than said metal monitor structure; and    wherein said metal monitor structure and said metal control structure have substantially identical resistances without metal failure of said metal monitor structure and a resistance difference upon metal failure of said metal monitor structure, said resistance difference signalling possible metal failure of said semiconductor wafer.     
     
     
       30. The metal test structure of claim 29, wherein said semiconductor wafer includes multiple integrated circuits, and wherein said plurality of test devices is disposed in a kerf region of said semiconductor wafer. 
     
     
       31. The metal test structure of claim 29, wherein at least some test devices of said plurality of test devices include metal monitor structures of different physical configuration than other metal monitor structures of other test devices of said plurality of test devices. 
     
     
       32. The metal test structure of claim 31, wherein each of said metal monitor structures of said plurality of test devices occupies at least two metallization levels on said semiconductor wafer. 
     
     
       33. The metal test structure of claim 29, wherein said semiconductor wafer includes multiple metallization levels, and wherein said plurality of test devices includes for each metallization level of said multiple metallization levels at least one test device having a metal monitor structure prone to metal failure in that metallization level. 
     
     
       34. A method for fabricating a test device for indicating possible metal failure of a semiconductor wafer, said method comprising the steps of: (a) predesigning a metal monitor structure and a metal control structure such that said metal monitor structure is prone to metal failure and said metal control structure is resistant to metal failure, such that said metal control structure is less prone to metal failure than said metal monitor structure, and such that said metal monitor structure and said metal control structure have substantially identical resistances without metal failure of said metal monitor structure and a resistance difference upon metal failure of said metal monitor structure, said resistance difference indicating possible metal failure of said semiconductor wafer; and   (b) fabricating said metal monitor structure and said metal control structure at an inactive region of said semiconductor wafer.   
     
     
       35. The method of claim 34, wherein said fabricating step (b) includes proceeding with said step (b) commensurate with fabricating of interconnect metallization at active regions of said semiconductor wafer. 
     
     
       36. The method of claim 34, further in combination with testing said semiconductor wafer for possible metal failure using said metal monitor structure and said metal control structure fabricated in said step (b). 
     
     
       37. The method of claim 36, wherein said testing includes determining a resistance of said metal monitor structure and a resistance of said metal control structure, said resistance determining including forcing a known current through said metal monitor structure and said metal control structure and simultaneously sensing voltages established thereacross.