Power semiconductor device comprising vertical double-diffused MOSFETS each having low on-resistance per unit area

Abstract

In a vertical double-diffused MOSFET comprising a semiconductor substrate of a first conductivity type, an epitaxial layer of the first conductivity type, and a gate insulating layer, a gate electrode coats the gate insulating layer. The gate electrode has a plurality of polygonal shaped opening windows and at least one slit shaped opening window. Each polygonal shaped opening window has a center positioned on each of lattice points of a two-dimensional square lattice comprising a plurality of unit cells. Each slit shaped opening window is laid on a straight line connecting two centers of two polygonal shaped opening windows which are obliquely adjacent to one another. A first insulating layer is formed on an upper surface of the gate electrode. Second insulating layers are formed on side walls of the gate electrode. A base region of a second conductivity type having a base junction depth is formed in the surface of the epitaxial layer. The base region is self-aligned to the polygonal shaped opening windows and the slit shaped opening window. A source region of the first conduction type has a source junction depth shallower than the base junction depth. The source region has an inner edge self-aligned to both of the polygonal shaped opening windows and the slit shaped opening window and an inner edge spaced apart from the polygonal shaped open windows at a predetermined width.

What is claimed is: 
     
       1. A vertical double-diffused metal oxide semiconductor field effect transistor (MOSFET) comprising: a semiconductor substrate of a first conductivity type having a main surface and a bottom surface opposite to the main surface, said semiconductor substrate being doped with impurities of the first conductivity type that has substrate impurity concentration;   an epitaxial layer of the first conductivity type formed on the main surface of said semiconductor substrate, said epitaxial layer being doped with impurities of the first conductivity type that has epitaxial impurity concentration lower than the substrate impurity concentration of said semiconductor substrate;   a gate insulating layer formed on a surface of said epitaxial layer;   a gate electrode coating said gate insulating layer, said gate electrode having a plurality of polygonal shaped opening windows each of which has a center positioned on each of lattice points of a two-dimensional square lattice comprising a plurality of unit cells, each of the unit cells being defined by two pairs of opposed sides, one pair of the opposed sides extending along a first direction and being apart from one another at a predetermined distance, another pair of the opposed sides extending along a second direction orthogonal to the first direction and being apart from one another at the predetermined distance, said gate electrode having at least one slit shaped opening window which is laid on a straight line connecting two centers of two polygonal shaped opening windows which are obliquely adjacent to one another;   a first insulating layer formed on an upper surface of said gate electrode;   second insulating layers formed on side walls of said gate electrode;   a base region of a second conductivity type which is opposite to the first conductivity type, said base region having a predetermined base junction depth, said base region being formed in the surface of said epitaxial layer, said base region being self-aligned to the polygonal shaped opening windows and the slit shaped opening window;   a source region of the first conductivity type having a source junction depth shallower than the base junction depth, said source region having an outer edge self-aligned to both of the polygonal shaped opening windows and the slit shaped opening window and an inner edge spaced apart from edges of the polygonal shaped opening windows at a predetermined width;   a source electrode covering said first and said second insulating layers, said source electrode being directly connected to said source region with said source electrode short-circuited to said base region in at least the polygonal shaped opening windows; and   a drain electrode formed on the bottom surface of said semiconductor substrate.   
     
     
       2. A vertical double-diffused MOSFET as claimed in claim 1, wherein said semiconductor substrate is a silicon substrate. 
     
     
       3. A vertical double-diffused MOSFET as claimed in claim 1, wherein said gate insulating layer is a gate oxide layer. 
     
     
       4. A vertical double-diffused MOSFET as claimed in claim 1, wherein each of the polygonal shaped opening windows comprises a pair of opposed sides in parallel with the first direction and another pair of opposed sides in parallel with the second direction. 
     
     
       5. A vertical double-diffused MOSFET as claimed in claim 4, wherein each of said polygonal shaped opening windows is square in configuration. 
     
     
       6. A vertical double-diffused MOSFET as claimed in claim 4, wherein each of said polygonal shaped opening windows is octagonal in configuration. 
     
     
       7. A vertical double-diffused MOSFET as claimed in claim 1, said gate electrode having a plurality of slit shaped opening windows, wherein one of the polygonal shaped opening windows is connected through two slit shaped opening windows to two of the polygonal shaped opening windows that are obliquely adjacent to the one of the polygonal shaped opening windows. 
     
     
       8. A vertical double-diffused MOSFET as claimed in claim 1, wherein said source electrode is directly connected to said source region in the slit shaped opening window. 
     
     
       9. A vertical double-diffused MOSFET as claimed in claim 1, further comprising a plurality of base leading electrodes of the second conductivity type which are directly connected to said base region in central portions of the respective polygonal shaped opening windows through direct contact holes, said source electrode being connected to said base regions through said base leading electrodes, each of said base leading electrodes having a side wall on which said second insulating layer is formed. 
     
     
       10. A vertical double-diffused MOSFET as claimed in claim 9, wherein each of said leading electrodes consists of a polysilicon layer. 
     
     
       11. A vertical double-diffused metal oxide semiconductor field effect transistor (MOSFET) comprising: a semiconductor substrate of a first conductivity type having a main surface and a bottom surface opposite to the main surface, said semiconductor substrate being doped with impurities of the first conductivity type that has substrate impurity concentration;   an epitaxial layer of the first conductivity type formed on the main surface of said semiconductor substrate, said epitaxial layer being doped with impurities of the first conductivity type that has epitaxial impurity concentration lower than the substrate impurity concentration of said semiconductor substrate;   a gate insulating layer formed on a surface of said epitaxial layer;   a gate electrode coating said gate insulating layer, said gate electrode having a pair of square shaped opening windows which are obliquely adjacent to one another and a slit shaped opening window connecting the pair of square shaped opening windows;   a first insulating layer formed on an upper surface of said gate electrode;   second insulating layers formed on side walls of said gate electrode;   a base region of a second conductivity type which is opposite to the first conductivity type, said base region being formed in the surface of said epitaxial layer, said base region being self-aligned to the pair of square shaped opening windows and the slit shaped opening window;   a source region of the first conductivity type having a source junction depth shallower than the base junction depth, said source region having an outer edge self-aligned to both of the square shaped opening windows and the slit shaped opening window and an inner edge spaced apart from edges of the square shaped opening windows at a predetermined width;   a source electrode covering said first and said second insulating layers, said source electrode being directly connected to said source region with said source electrode short-circuited to said base region in the pair of square shaped opening windows; and   a drain electrode formed on the bottom surface of said semiconductor substrate.   
     
     
       12. A vertical double-diffused MOSFET as claimed in claim 11, wherein said semiconductor substrate is a silicon substrate. 
     
     
       13. A vertical double-diffused MOSFET as claimed in claim 11, wherein said gate insulating layer is a gate oxide layer. 
     
     
       14. A vertical double-diffused metal oxide semiconductor field effect transistor (MOSFET) comprising: a semiconductor substrate of a first conductivity type having a main surface and a bottom surface opposite to the main surface, said semiconductor substrate being doped with impurities of the first conductivity type that has substrate impurity concentration;   an epitaxial layer of the first conductivity type formed on the main surface of said semiconductor substrate, said epitaxial layer being doped with impurities of the first conductivity type that has epitaxial impurity concentration lower than the substrate impurity concentration of said semiconductor substrate;   a gate insulating layer formed on a surface of said epitaxial layer;   a gate electrode coating said gate insulating layer, said gate electrode having a pair of square shaped opening windows which are obliquely adjacent to one another and a slit shaped opening window connecting the pair or square shaped opening windows;   a first insulating layer formed on an upper surface of said gate electrode;   second insulating layers formed on side walls of said gate electrode;   a base region of a second conductivity type which is opposite to the first conductivity type, said base region having a base junction depth, said base region being formed in the surface of said epitaxial layer, said base region being self-aligned to the pair of square shaped opening windows and the slit shaped opening window;   a source region of the first conductivity type having a source junction depth shallower than the base junction depth, said source region having an outer edge self-aligned to both of the square shaped opening windows and the slit shaped opening window and an inner edge spaced apart from edges of the square shaped opening windows at a predetermined width;   a source electrode covering said first and said second insulating layers, said source electrode being directly connected to said source region with said source electrode short-circuited to said base region in the pair of square shaped opening windows, said source electrode being directly connected to said source region in the slit shaped opening window; and   a drain electrode formed on the bottom surface of said semiconductor substrate.   
     
     
       15. A vertical double-diffused MOSFET as claimed in claim 14, wherein said semiconductor substrate is a silicon substrate. 
     
     
       16. A vertical double-diffused MOSFET as claimed in claim 14, wherein said gate insulating layer is a gate oxide layer. 
     
     
       17. A vertical double-diffused metal oxide semiconductor field effect transistor (MOSFET) comprising: a semiconductor substrate of a first conductivity type having a main surface and a bottom surface opposite to the main surface, said semiconductor substrate being doped with impurities of the first conduction type that has substrate impurity concentration;   an epitaxial layer of the first conductivity type formed on the main surface of said semiconductor substrate, said epitaxial layer being doped with impurities of the first conductivity type that has epitaxial impurity concentration lower than the substrate impurity concentration of said semiconductor substrate;   a gate insulating layer formed on a surface of said epitaxial layer;   a gate electrode coating said gate insulating layer, said gate electrode having a pair of octagonal shaped opening windows which are obliquely adjacent to one another and a slit shaped opening window connecting the pair of octagonal shaped opening windows;   a first insulating layer formed on an upper surface of said gate electrode;   second insulating layers formed on side walls of said gate electrode;   a base region of a second conductivity type which is opposite to the first conductivity type, said base region having a base junction depth, said base region being formed in the surface of said epitaxial layer, said base region being self-aligned to the pair of octagonal shaped opening windows and the slit shaped opening window;   a source region of the first conductivity type having a source junction depth shallower than the base junction depth, said source region having an outer edge self-aligned to both of the octagonal shaped opening windows and the slit shaped opening window and an inner edge spaced apart from edges of the octagonal shaped opening windows at a predetermined width;   a source electrode covering said first and said second insulating layers, said source electrode being directly connected to said source region with said source electrode short-circuited to said base region in the pair of octagonal shaped opening windows; and   a drain electrode formed on the bottom surface of said semiconductor substrate.   
     
     
       18. A vertical double-diffused MOSFET as claimed in claim 17, wherein said semiconductor substrate is a silicon substrate. 
     
     
       19. A vertical double-diffused MOSFET as claimed in claim 17, wherein said gate insulating layer is a gate oxide layer. 
     
     
       20. A vertical double-diffused metal oxide semiconductor field effect transistor (MOSFET) comprising: a semiconductor substrate of a first conductivity type having a main surface and a bottom surface opposite to the main surface, said semiconductor substrate being doped with impurities of the first conductivity type that has substrate impurity concentration;   an epitaxial layer of the first conductivity type formed on the main surface of said semiconductor substrate, said epitaxial layer being doped with impurities of the first conductivity type that has epitaxial impurity concentration lower than the substrate impurity concentration of said semiconductor substrate;   a gate insulating layer formed on a surface of said epitaxial layer;   a gate electrode coating said gate insulating layer, said gate electrode having a plurality of square shaped opening windows each of which has a center positioned on each of lattice points of a two-dimensional square lattice comprising a plurality of unit cells, each of the unit cells being defined by two pairs of opposed sides, one pair of the opposed sides extending along a first direction and being apart from one another at a predetermined distance, another pair of the opposed sides extending along a second direction orthogonal to the first direction and being apart from one another at the predetermined distance, said gate electrode having a plurality of slit shaped opening windows connecting two centers of two of said square shaped opening windows that are obliquely adjacent to one another;   a plurality of base leading electrodes of a second conductivity type which is opposite to the first conductivity type, said base leading electrodes being disposed in central portions of the respective square shaped opening windows;   a first insulating layer formed on an upper surface of said gate electrode;   second insulating layers formed on side walls of both of said gate electrode and said base leading electrodes;   a base region of a second conductivity type having a base junction depth, said base region being formed in the surface of said epitaxial layer, said base region being self-aligned to the square shaped opening windows and the slit shaped opening window, said base region being directly connected to said base leading electrodes through respective direct contact holes;   a source region of the first conductivity type having a source junction depth shallower than the base junction depth, said source region having an outer edge self-aligned to both of the square shaped opening windows and the slit shaped opening window and an inner edge spaced apart from edges of the square shaped opening windows at a predetermined width;   a source electrode covering said first and said second insulating layers and said base leading electrodes, said source electrode being directly connected to said source region with said source electrode short-circuited to said base region through said base leading electrodes, said source electrode being directly connected to said source region in the slit shaped opening window; and   a drain electrode formed on the bottom surface of said semiconductor substrate.   
     
     
       21. A vertical double-diffused MOSFET as claimed in claim 20, wherein said semiconductor substrate is a silicon substrate. 
     
     
       22. A vertical double-diffused MOSFET as claimed in claim 20, wherein said gate insulating layer is a gate oxide layer. 
     
     
       23. A vertical double-diffused MOSFET as claimed in claim 20, wherein each of said base leading electrodes consists of a polysilicon layer. 
     
     
       24. A power semiconductor device having a plurality of vertical double-diffused metal oxide semiconductor field effect transistors (MOSFETs) which are connected to each other in parallel, said power semiconductor device comprising: a semiconductor substrate of a first conductivity type having a main surface and a bottom surface opposite to the main surface, said semiconductor substrate being doped with impurities of the first conductivity type that has substrate impurity concentration;   an epitaxial layer of the first conductivity type formed on the main surface of said semiconductor substrate, said epitaxial layer having a predetermined thickness and being doped with impurities of the first conductivity type that has epitaxial impurity concentration lower than the substrate impurity concentration of said semiconductor substrate;   a gate insulating layer formed on a surface of said epitaxial layer;   a gate electrode coating said gate insulating layer, said gate electrode having a plurality of polygonal shaped opening windows each of which has a center positioned on each of lattice points of a two-dimensional square lattice comprising a plurality of unit cells, each of the unit cells being defined by two pairs of opposed sides, one pair of the opposed sides extending along a first direction and being apart from one another at a predetermined distance, another pair of the opposed sides extending along a second direction orthogonal to the first direction and being apart from one another at the predetermined distance, said gate electrode having a plurality of slit shaped opening windows each of which is laid on a straight line connecting two centers of two polygonal shaped opening windows which are obliquely adjacent to one another;   a first insulating layer formed on an upper surface of said gate electrode;   second insulating layers formed on side walls of said gate electrode;   a plurality of base regions of a second conductivity type which is opposite to the first conductivity type, each of said base regions having a base junction depth, said base regions being formed in the surface of said epitaxial layer, each of said base regions being self-aligned to the polygonal shaped opening windows and the slit shaped opening windows;   a plurality of source regions of the first conductivity type having a source junction depth shallower than the base junction depth, said source region having an outer edge self-aligned to both of the polygonal shaped opening windows and the slit shaped opening windows and an inner edge spaced apart from edges of the polygonal shaped opening windows at a predetermined width;   a source electrode covering said first and said second insulating layers, said source electrode being directly connected to said source regions with said source electrode short-circuited to said base regions in at least the polygonal shaped opening windows; and   a drain electrode formed on the bottom surface of said semiconductor substrate.   
     
     
       25. A power semiconductor device as claimed in claim 24, wherein said semiconductor substrate is a silicon substrate. 
     
     
       26. A power semiconductor device as claimed in claim 24, wherein said gate insulating layer is a gate oxide layer. 
     
     
       27. A power semiconductor device as claimed in claim 24, wherein each of the polygonal shaped opening windows comprises a pair of opposed sides in parallel with the first direction and another pair of opposed sides in parallel with the second direction. 
     
     
       28. A power semiconductor device as claimed in claim 27, wherein each of said polygonal shaped opening windows is square in configuration. 
     
     
       29. A power semiconductor device as claimed in claim 27, wherein each of said polygonal shaped opening windows is octagonal in configuration. 
     
     
       30. A power semiconductor device as claimed in claim 24, wherein one of the polygonal shaped opening windows is connected through two slit shaped opening windows to two of the polygonal shaped opening windows that are obliquely adjacent to the one of the polygonal shaped opening windows. 
     
     
       31. A power semiconductor device as claimed in claim 24, wherein said source electrode is directly connected to said source regions in the slit shaped opening windows. 
     
     
       32. A power semiconductor device as claimed in claim 24, further comprising a plurality of base leading electrodes of the second conductivity type which are directly connected to said base regions in central portions of the respective polygonal shaped opening windows through direct contact holes, each of said base leading electrodes having a side wall on which said second insulating layer is formed, whereby said source electrode is connected to said base regions through said base leading electrodes. 
     
     
       33. A power semiconductor device as claimed in claim 32, wherein each of said base leading electrodes consists of a polysilicon layer. 
     
     
       34. A power semiconductor device having a plurality of vertical double-diffused metal oxide semiconductor field effect transistors (MOSFETs) which are connected to each other in parallel, said power semiconductor device comprising: a semiconductor substrate of a first conductivity type having a main surface and a bottom surface opposite to the main surface, said semiconductor substrate being doped with impurities of the first conductivity type that has substrate impurity concentration;   an epitaxial layer of the first conductivity type formed on the main surface of said semiconductor substrate, said epitaxial layer having a predetermined thickness and being doped with impurities of the first conductivity type that has epitaxial impurity concentration lower than the substrate impurity concentration of said semiconductor substrate;   a gate insulating layer formed on a surface of said epitaxial layer;   a gate electrode coating said gate insulating layer, said gate electrode having a plurality of square shaped opening windows each of which has a center positioned on each of lattice points of a two-dimensional square lattice comprising a plurality of unit cells, each of the unit cells being defined by two pairs of opposed sides, one pair of the opposed sides extending along a first direction and being apart from one another at a predetermined distance, another pair of the opposed sides extending along a second direction orthogonal to the first direction and being apart from one another at the predetermined distance, said gate electrode having a plurality of slit shaped opening windows each of which is laid on a straight line connecting two centers of two of the square shaped opening windows that are obliquely adjacent to one another;   a first insulating layer formed on an upper surface of said gate electrode;   a plurality of second insulating layers formed on side walls of said gate electrode;   a plurality of base regions of a second conductivity type which is opposite to the first conductivity type, each of said base regions having a base junction depth, said base regions being formed in the surface of said epitaxial layer, each of said base regions being self-aligned to two of the square shaped opening windows and one of the slit shaped opening windows;   a plurality of source regions of the first conductivity type having a source junction depth shallower than the base junction depth, each of said source regions having an outer edge self-aligned to the two of the square shaped opening windows and the one of the slit shaped opening windows and an inner edge spaced apart from edges of the two of the square shaped opening windows at a predetermined width;   a source electrode covering said first and said second insulating layers, said source electrode being directly connected to said source regions with said source electrode short-circuited to said base regions in the square shaped opening windows; and   a drain electrode formed on the bottom surface of said semiconductor substrate.   
     
     
       35. A power semiconductor device as claimed in claim 34, wherein said semiconductor substrate is a silicon substrate. 
     
     
       36. A power semiconductor device as claimed in claim 34, wherein said gate insulating layer is a gate oxide layer. 
     
     
       37. A power semiconductor device having a plurality of vertical double-diffused metal oxide semiconductor field effect transistors (MOSFETs) which are connected to each other in parallel, said power semiconductor device comprising: a semiconductor substrate of a first conductivity type having a main surface and a bottom surface opposite to the main surface, said semiconductor substrate being doped with impurities of the first conductivity type that has substrate impurity concentration;   an epitaxial layer of the first conductivity type formed on the main surface of said semiconductor substrate, said epitaxial layer having a predetermined thickness and being doped with impurities of the first conductivity type that has epitaxial impurity concentration lower than the substrate impurity concentration of said semiconductor substrate;   a gate insulating layer formed on a surface of said epitaxial layer;   a gate electrode coating said gate insulating layer, said gate electrode having a plurality of square shaped opening windows each of which has a center positioned on each of lattice points of a two-dimensional square lattice comprising a plurality of unit cells, each of the unit cells being defined by two pairs of opposed sides, one pair of the opposed sides extending along a first direction and being apart from one another at a predetermined distance, another pair of the opposed sides extending along a second direction orthogonal to the first direction and being apart from one another at the predetermined distance, said gate electrode having a plurality of slit shaped opening windows each of which is laid on a straight line connecting two centers of two of the square shaped opening windows which are obliquely adjacent to one another;   a first insulating layer formed on an upper surface of said gate electrode;   a plurality of second insulating layers formed on side walls of said gate electrode;   a plurality of base regions of a second conductivity type which is opposite to the first conductivity type, each of said base regions having a base junction depth, said base regions being formed in the surface of said epitaxial layer, each of said base regions being self-aligned to two of the square shaped opening windows and one of the slit shaped opening windows;   a plurality of source regions of the first conductivity type having a source junction depth shallower than the base junction depth, each of said source regions having an outer edge self-aligned to the two of the square shaped opening windows and the one of the slit shaped opening windows and an inner edge spaced apart from edges of the two of the square shaped opening windows at a predetermined width;   a source electrode covering said first and said second insulating layers, said source electrode being directly connected to said source regions with said source electrode short-circuited to said base regions in the square shaped opening windows; said electrode being directly connected to said source regions in the slit shaped opening window; and   a drain electrode formed on the bottom surface of said semiconductor substrate.   
     
     
       38. A power semiconductor device as claimed in claim 37, wherein said semiconductor substrate is a silicon substrate. 
     
     
       39. A power semiconductor device as claimed in claim 37, wherein said gate insulating layer is a gate oxide layer. 
     
     
       40. A power semiconductor device having a plurality of vertical double-diffused metal oxide semiconductor field effect transistors (MOSFETs) which are connected to each other in parallel, said power semiconductor device comprising: a semiconductor substrate of a first conductivity type having a main surface and a bottom surface opposite to the main surface, said semiconductor substrate being doped with impurities of the first conductivity type that has substrate impurity concentration;   an epitaxial layer of the first conductivity type formed on the main surface of said semiconductor substrate, said epitaxial layer having a predetermined thickness and being doped with impurities of the first conductivity type that has epitaxial impurity concentration lower than the substrate impurity concentration of said semiconductor substrate;   a gate insulating layer formed on a surface of said epitaxial layer;   a gate electrode coating said gate insulating layer, said gate electrode having a plurality of octagonal shaped opening windows each of which has a center positioned on each of lattice points of a two-dimensional square lattice comprising a plurality of unit cells, each of the unit cells being defined by two pairs of opposed sides, one pair of the opposed sides extending along a first direction and being apart from one another at a predetermined distance, another pair of the opposed sides extending along a second direction orthogonal to the first direction and being apart from one another at the predetermined distance, said gate electrode having a plurality of slit shaped opening windows each of which is laid on a straight line connecting two centers of two of the octagonal shaped opening windows that are obliquely adjacent to one another;   a first insulating layer formed on an upper surface of said gate electrode;   a plurality of second insulating layers formed on side walls of said gate electrode;   a plurality of base regions of a second conductivity type which is opposite to the first conductivity type, each of said base regions having a base junction depth, said base regions being formed in the surface of said epitaxial layer, each of said base regions being self-aligned to two of the octagonal shaped opening windows and one of the slit shaped opening windows;   a plurality of source regions of the first conductivity type having a source junction depth shallower than the base junction depth, each of said source regions having an outer edge self-aligned to the two of the octagonal shaped opening windows and the one of the slit shaped opening windows and an inner edge spaced apart from edges of the two of the octagonal shaped opening windows at a predetermined width;   a source electrode covering said first and said second insulating layers, said source electrode being directly connected to said source regions with said source electrode short-circuited to said base regions in the octagonal shaped opening windows; and   a drain electrode formed on the bottom surface of said semiconductor substrate.   
     
     
       41. A power semiconductor device as claimed in claim 40, wherein said semiconductor substrate is a silicon substrate. 
     
     
       42. A power semiconductor device as claimed in claim 40, wherein said gate insulating layer is a gate oxide layer. 
     
     
       43. A power semiconductor device having a plurality of vertical double-diffused metal oxide semiconductor field effect transistors (MOSFETs) which are connected to each other in parallel, said power semiconductor device comprising: a semiconductor substrate of a first conductivity type having a main surface and a bottom surface opposite to the main surface, said semiconductor substrate being doped with impurities of the first conductivity type that has substrate impurity concentration;   an epitaxial layer of the first conductivity type formed on the main surface of said semiconductor substrate, said epitaxial layer having a predetermined thickness and being doped with impurities of the first conductivity type that has epitaxial impurity concentration lower than the substrate impurity concentration of said semiconductor substrate;   a gate insulating layer formed on a surface of said epitaxial layer;   a gate electrode coating said gate insulating layer, said gate electrode having a plurality of square shaped opening windows each of which has a center positioned on each of lattice points of a two-dimensional square lattice comprising a plurality of unit cells, each of the unit cells being defined by two pairs of opposed sides, one pair of the opposed sides extending along a first direction and being apart from one another at a predetermined distance, another pair of the opposed sides extending along a second direction orthogonal to the first direction and being apart from one another at a predetermined distance, said gate electrode having a plurality of slit shaped opening windows each of which is laid on a straight line connecting two centers of two of said square shaped opening windows that are obliquely adjacent to one another;   a plurality of base leading electrodes of a second conductivity type which is opposite to the first conductivity type, said base leading electrodes being disposed in central portions of the respective square shaped opening windows;   a first insulating layer formed on an upper surface of said gate electrode;   a plurality of second insulating layers formed on side walls of said gate electrode and said base leading electrodes;   a plurality of base regions of the second conductivity type each of which has a predetermined base junction depth, said base regions being formed in the surface of said epitaxial layer, each of said base regions being self-aligned to at least three of the square shaped opening windows and at least two of the slit shaped opening windows, said base regions being directly connected to said base leading electrodes through respective direct contact holes;   a plurality of source regions of the first conductivity type each of which has a source junction depth shallower than the base junction depth, each of the said source regions having an outer edge self-aligned to the at least three of the square shaped opening windows and the at least two of the slit shaped opening windows and an inner edge spaced apart from edges of the at least three of the square shaped opening windows at a predetermined width;   a source electrode covering said first and said second insulating layers and said base leading electrodes, said source electrode being directly connected to said source regions with said source electrode short-circuited to said base regions through said base leading electrodes in the square shaped opening windows, said source electrode being directly connected to said source regions in the slit shaped opening windows; and   a drain electrode formed on the bottom surface of said semiconductor substrate.   
     
     
       44. A power semiconductor device as claimed in claim 43, wherein said semiconductor substrate is a silicon substrate. 
     
     
       45. A power semiconductor device as claimed in claim 43, wherein said gate insulating layer is a gate oxide layer. 
     
     
       46. A power semiconductor device as claimed in claim 43, wherein each of said base leading electrodes consists of a polysilicon layer.