Bus-to-bus bridge for a multiple bus information handling system that optimizes data transfers between a system bus and a peripheral bus

Abstract

Hardware logic within a host bridge that connects a system bus to a peripheral bus using PCI bus architecture or a peripheral bus that uses a bus architecture similar to PCI. The hardware optimizes the speed at which data transfers are accomplished between the buses while translating the data transfers between the different architectures of the two buses.

We claim: 
     
       1. An information handling system, comprising: a system bus having a slave memory device attached thereto;   a host bridge for connecting said system bus to a peripheral bus; and   a master peripheral device attached to said peripheral bus for initiating a burst transfer of a plurality of data strings between said master peripheral device and said slave memory device over said host bridge, each of said plurality of data strings having a predetermined bit width defining a plurality of data substrings;   said peripheral bus including an enable/non-enable signal for each of said plurality of data strings which indicates which of said data substrings contain valid data and which of said data substrings contain invalid data;   said host bridge including system bus interface logic which is responsive to said enable/non-enable signals on said peripheral bus to (i) detect whether said plurality of data strings to be burst transferred between said peripheral bus and said system bus are system bus incompatible in that at least one data string of said plurality of data strings contains at least one invalid data substring, and (ii) convert system bus incompatible data strings into one or more system bus compatible data strings, wherein each of said one or more system bus compatible data strings does not contain any invalid data substring, before said data is transferred between said host bridge and said system bus.   
     
     
       2. The information handling system of claim 1, wherein said host bridge further includes a buffer for temporarily storing read data being transferred from a system bus address to said buffer or write data being transferred from said buffer to a system bus address. 
     
     
       3. The information handling system of claim 2, wherein said system bus interface logic includes increment logic for converting said system bus incompatible data strings into one or more of said system bus compatible data strings, said increment logic detecting and disregarding addresses within a particular data string which correspond to invalid data substrings within the data string. 
     
     
       4. The information handling system of claim 3, wherein said increment logic includes (i) a first adder for providing a first increment system bus address immediately after either write data is written to said system bus address across said system bus or read data is read from said system bus address across said system bus, said first increment system bus address being incremented one address from said system bus address, and (ii) a second adder for providing a second increment system bus address immediately after either write data is written to said system bus address across said system bus or read data is read from said system bus address across said system bus, said second increment system bus address being incremented two addresses from said system bus address. 
     
     
       5. The information handling system of claim 4, wherein said increment logic further includes a multiplexor for receiving first and second outputs from said first and second adders, respectively, and outputting only one of said first and second outputs. 
     
     
       6. The information handling system of claim 1, wherein said peripheral bus conforms to PCI bus architecture. 
     
     
       7. The information handling system of claim 6, wherein both said PCI bus and said system bus transmit data in 32-bit bandwidths. 
     
     
       8. A host bridge for connecting a system bus, having a slave memory device attached thereto, to a peripheral bus, having a master peripheral device attached thereto for initiating a burst transfer of a plurality of data strings between the master peripheral device and the slave memory device over the host bridge, each of the plurality of data strings having a predetermined bit width defining a plurality of data substrings; the peripheral bus including an enable/non-enable signal for each of the plurality of data strings which indicates which of the data substrings contain valid data and which of the data substrings contain invalid data; said host bridge comprising: detection logic responsive to the enable/non-enable signals on the peripheral bus for detecting whether the plurality of data strings to be burst transferred between the peripheral bus and the system bus are system bus incompatible in that at least one data string of the plurality of data strings contains at least one invalid data substring, and   conversion logic for converting system bus incompatible data strings into one or more system bus compatible data strings, wherein each of said one or more system bus compatible data strings does not contain any invalid data substring, before said data is transferred from the host bridge to the system bus.   
     
     
       9. The host bridge of claim 8, further comprising a buffer for temporarily storing read data being transferred from a system bus address to said buffer or write data being transferred from said buffer to a system bus address. 
     
     
       10. The host bridge of claim 9, further comprising increment logic for converting said system bus incompatible data strings into one or more of said system bus compatible data strings, said increment logic detecting and disregarding addresses within a particular data string which correspond to invalid data substrings within the data string. 
     
     
       11. The host bridge of claim 10, wherein said increment logic includes (i) a first adder for providing a first increment system bus address immediately after either write data is written to the system bus address across the system bus or read data is read from the system bus address across the system bus, said first increment system bus address being incremented one address from the system bus address, and (ii) a second adder for providing a second increment system bus address immediately after either write data is written to the system bus address across the system bus or read data is read from the system bus address across the system bus, said second increment system bus address being incremented two addresses from the system bus address. 
     
     
       12. The host bridge of claim 11, wherein said increment logic further includes a multiplexor for receiving first and second outputs from said first and second adders, respectively, and outputting only one of said first and second outputs.