System for speculatively executing instructions wherein mispredicted instruction is executed prior to completion of branch processing

Abstract

A processing system and method of operation are provided, In response to a branch instruction, a first instruction is processed so that a storage location is associated with the first instruction prior to execution of the branch instruction. In response to execution of the branch instruction, a second instruction is processed independent of information previously stored in the storage location so that the storage location is associated with the second instruction prior to completion of the branch instruction.

What is claimed is: 
     
       1. A method of operating a processing system, comprising the steps of: initiating a plurality of processing stages of a branch instruction;   in response to initiating at least one of said processing stages of said branch instruction, initiating a plurality of processing stages of a first instruction;   in response to an execution processing stage of said first instruction, selectively storing first information in a storage location prior to finishing an execution processing stage of said branch instruction;   in response to said execution processing stage of said branch instruction indicating said first instruction is not to be executed, initiating a plurality of processing stages of a second instruction; and   in response to an execution processing stage of said second instruction, selectively storing second information in said storage location prior to a completion processing of said branch instruction, independent of information previously stored in said storage location.   
     
     
       2. The method of claim 1 wherein said storage location is a rename buffer storage location. 
     
     
       3. The method of claim 1 wherein said storage location is a reorder buffer storage location. 
     
     
       4. The method of claim 1 wherein said branch instruction is a conditional branch instruction. 
     
     
       5. The method of claim 1 wherein said first and second instructions respectively belong to first and second target sequences of instructions of said branch instruction. 
     
     
       6. The method of claim 1 and further comprising the steps of: after initiating said processing of said branch instruction, initiating a plurality of processing stages of an additional branch instructions.   in response to initiating at least one of said processing stages of said additional branch instruction, initiating a plurality of processing stages of a third instruction;   in response to an execution processing stage of said third instruction, selectively storing third information in an additional storage location prior to finishing an execution processing stage of said additional branch instruction;   in response to said execution processing stage of said additional branch instruction indicating said third instruction is not to be executed, initiating a plurality of processing stages of a fourth instruction; and   in response to an execution processing stage of said fourth instruction, selectively storing fourth information in said additional storage location prior to a completion processing stage of said additional branch instruction and prior to finishing said execution processing stage of said branch instructions independent of information previously stored in said additional storage location.   
     
     
       7. A processing system, comprising: at least one storage location; and   circuitry for:   initiation a plurality of processing stages of a branch instruction;   initiating a plurality processing stages of a first instruction in response to initiating at least one of said processing stage of said branch instruction;   in response to an execution processing stage of said first instruction, selectively storing first information in said storage location prior to finishing an execution processing stage of said branch instruction;   initiating a plurality of processing stage of a second instruction in response to said execution processing stage of said branch instruction indicating said first instruction is not to be executed; and   in response to an execution processing stage of said second instruction, selectively storing second information in said storage location prior to B completion processing stage of said branch instruction, independent of information previously stored in said storage location.   
     
     
       8. The system of claim 7 wherein said storage location is a rename buffer storage location. 
     
     
       9. The system of claim 7 wherein said storage location is a reorder buffer storage location. 
     
     
       10. The system of claim 7 wherein said branch instruction is a conditional branch instruction. 
     
     
       11. The system of claim 7 wherein said first and second instructions respectively belong to first and second target sequences of instructions of said branch instruction. 
     
     
       12. The system of claim 7 wherein said circuitry is operable to: after initiating said processing stages of said branch instruction, initiate a plurality of processing stages of an additional branch instruction;   initiate a plurality of processing stages of a third instruction in response to initiating at least one of said processing stages of said additional branch instruction;   in response to an execution processing stage of said third instruction, selectively store third information in an additional storage location prior to finishing an execution processing stage of said additional branch instruction;   initiate a plurality of processing stages of a fourth instruction in response to said execution processing stage of said additional branch instruction indicating said third instruction is not to be executed; and   in response to an execution processing stage of said fourth instruction, selectively store fourth information in said additional storage location prior to a completion processing stage of said additional branch instruction and prior to finishing said execution processing stage of said branch instruction, independent of information previously stored in said additional storage location.