Dynamic management of snoop granularity for a coherent asynchronous DMA cache

Abstract

A system and method dynamically changes the snoop comparison granularity between a sector and a page, depending upon the state (active or inactive) of a direct memory access (DMA) I/O device which is writing to a device on the system bus asynchronously when compared to the CPU clock. By using page address granularity, erroneous snoop hits will not occur, since potentially invalid sector addresses are not used during the snoop comparison. Sector memory addresses may be in a transition state at the time when the CPU clock determines a snoop comparison is to occur, because this sector address has been requested by a device operating asynchronously with the CPU clock. Once the asynchronous device becomes inactive the system dynamically returns to a page and sector address snoop comparison granularity.

We claim: 
     
       1. A method of maintaining cache coherency in a system using a snooping protocol wherein a snoop comparison, occurs at a time based on a CPU clock, comprising the steps of: requesting, by a busmaster device, ownership of data from a memory by presenting an address having a page portion and a sector portion;   actively accessing said data in an internal cache of a first device asynchronously with said CPU clock; and   exclusively using the page portion of said address to implement said snoop comparison during the time when said internal cache is being actively accessed.   
     
     
       2. A method according to claim 1 further comprising the step of preventing another device from obtaining access to said data when said data is being actively accessed. 
     
     
       3. A method according to claim 2 further comprising the step of using the page portion and the sector portion of said address to implement said snoop comparison during the time when said internal cache is not being actively accessed. 
     
     
       4. A method according to claim 3 further comprising the step of invalidating said data in said first device upon determining that another device has requested said data during the time when the internal cache is not being actively accessed. 
     
     
       5. A data processing system that maintains cache coherency using a snooping protocol wherein a snoop comparison, occurs at a time based on a CPU clock, comprising: means for requesting ownership of data from a memory by presenting an address having a page portion and a sector portion;   means for actively accessing said data in an internal cache of a first device asynchronously with said CPU clock; and   means for exclusively using the page portion of said address to implement said snoop comparison during the time when said internal cache is being actively accessed.   
     
     
       6. A system according to claim 5 further comprising means for preventing another device from obtaining access to said data when said data is being actively accessed. 
     
     
       7. A system according to claim 6 further comprising means for using the page portion and the sector portion of said address to implement said snoop comparison during the time when said internal cache is not being actively accessed. 
     
     
       8. A system according to claim 7 further comprising means for invalidating said data in said first device upon determining that another device has requested said data during the time when the internal cache is not being actively accessed. 
     
     
       9. A system according to claim 8 wherein said first device is an input/output controller that provides an interface between a system bus and an input/output bus. 
     
     
       10. A system according to claim 9 wherein said means for actively accessing is an input/output device connected to said input/output controller which directly accesses data in said memory, independent of intervention by said CPU. 
     
     
       11. A system according to claim 5 further comprising means for dynamically changing the granularity used for said snoop comparison between said page portion exclusively, and said page portion and said sector portion, based on the state of said input/output device. 
     
     
       12. A system according to claim 11 wherein said means for dynamically changing comprises a logic circuit contained on said input/output controller. 
     
     
       13. A method of maintaining cache coherency in a system using a snooping protocol wherein a snoop comparison, occurs at a time based on a CPU clock, comprising the steps of: requesting, by a busmaster device, ownership of data from a memory by presenting an address having a page portion and a sector portion;   actively accessing said data in an internal cache of a first device asynchronously with said CPU clock;   using only the page portion of said address to implement said snoop comparison during the time when said internal cache is being actively accessed;   preventing another device from obtaining access to said data when said data is being actively accessed; and   using the page portion and the sector portion of said address to implement said snoop comparison during the time when said internal cache is not being actively accessed.   
     
     
       14. A method according to claim 13 further comprising the step of invalidating said data in said first device upon determining that another device has requested said data during the time when the internal cache is not being actively accessed. 
     
     
       15. A data processing system that maintains cache coherency using a snooping protocol wherein a snoop comparison, occurs at a time based on a CPU clock, comprising: means for requesting ownership of data from a memory by presenting an address having a page portion and a sector portion;   means for actively accessing said data in an internal cache of a first device asynchronously with said CPU clock;   means for using only the page portion of said address to implement said snoop comparison during the time when said internal cache is being actively accessed;   means for preventing another device from obtaining access to said data when said data is being actively accessed; and   means for using the page portion and the sector portion of said address to implement said snoop comparison during the time when said internal cache is not being actively accessed.   
     
     
       16. A system according to claim 15 further comprising means for invalidating said data in said first device upon determining that another device has requested said data during the time when the internal cache is not being actively accessed. 
     
     
       17. A system according to claim 16 wherein said first device is an input/output controller that provides an interface between a system bus and an input/output bus.