ECL-to-CMOS signal level converter

Abstract

A signal level converter is disclosed, for converting a signal having a first logic voltage swing characteristic to a signal having a second voltage swing characteristic. The converter comprises a level converting section and a differential circuit coupled thereto. The level converting section converts the supplied signal at the first logic voltage swing to an intermediate signal at a logic voltage swing different from the first voltage swing. The differential circuit 3, being supplied with the intermediate signal, produces an output signal at the second voltage swing level that corresponds to the potential difference between a high and low potential power supplies.

What is claimed is: 
     
       1. A signal level converter supplied with power from a high and a low potential power supplies, for converting a signal having a first logic voltage swing characteristic of an ECL level signal used in an ECL circuit to a signal having a second logic voltage swing characteristic of a MOS level signal used in a MOS circuit, the converter comprising: a level converting section for converting the supplied signal having a first logic voltage swing characteristic into an intermediate signal having a logic voltage swing characteristic different from the first voltage swing characteristic, said level converting section including a differential pair of bipolar junction transistors receiving said signal having a first logic voltage swing characteristic and wherein said intermediate signal is responsive to an output of said differential pair of bipolar junction transistors; and   a differential circuit including a differential pair of MOS transistors coupled to said level converting section and responsive to said intermediate signal, for generating an output signal at a second voltage swing characteristic.   
     
     
       2. The signal level converter according to claim 1, wherein said differential pair of MOS transistors have substantially similar conductivity characteristics, gates supplied with said intermediate signal, sources interconnected to one of said high and low potential power supplies, and one drain serving as a terminal to output the signal generated by said differential circuit; and wherein said differential circuit includes a current mirror circuit coupled to said differential pair of MOS transistors, said current mirror circuit comprising a pair of transistors having conductivity characteristics different from the conductivity characteristics of said MOS transistors.   
     
     
       3. The signal level converter according to claim 2, wherein said MOS transistors of said differential circuit are N channel MOS transistors. 
     
     
       4. The signal level converter according to claim 2, wherein said MOS transistors of said differential circuit are P channel MOS transistors. 
     
     
       5. The signal level converter according to claim 1 further comprising a current source circuit for said level converting section, said current source circuit including a current mirror circuit formed by a pair of MOS transistors. 
     
     
       6. The signal level converter of claim 1, wherein said second swing characteristic of said output signal of said differential circuit varies substantially between high and low potentials of said high and low potential power supplies.