Exception handling circuit and method

Abstract

A microprocessor circuit monitors addresses generated by the microprocessor to check for various address-exception conditions. Fetch-exception status bits are generated for each instruction byte to indicate whether an address-exception was detected for each respective byte address. Once fetches are performed, the fetch-exception status bits are fed to an instruction buffer with the corresponding instruction bytes, where they are maintained until execution. Decode logic of an instruction control unit analyzes the fetch-exception status bits upon execution, and generates exceptions before the corresponding exception-causing instructions are executed. Address-exceptions occurring as the result of operand accesses are handled immediately. The operand access causing the exception is aborted, and the decode of the following instruction is modified to generate a micro-interrupt. A micro-interrupt routine determines the cause of the interrupt, and generates the appropriate exception. For breakpoint exceptions on operand accesses, the micro-interrupt routine re-executes the breakpoint-causing instruction to completion before generating the appropriate exception.

What is claimed is: 
     
       1. A circuit that detects and handles fetch-exceptions for a microprocessor without slowing down the normal operation of said microprocessor, comprising: an exception circuit that monitors fetch-addresses generated by an execution unit of said microprocessor, and that performs fetch-exception checks on said fetch-addresses before said fetch-addresses are used by said microprocessor to fetch instructions from a memory, said exception circuit generating one or more fetch-exception status bits for each instruction byte of said instructions;   an instruction buffer that receives and stores said instructions fetched by said microprocessor, and that receives and stores said fetch-exception status bits corresponding to said instruction bytes of said instructions, said instruction bytes and said corresponding fetch-exception status bits being held by said instruction buffer until said instructions are executed; and   an instruction control unit that receives said instruction bytes and said corresponding fetch-exception status bits, and that generates micro-instructions based on said instruction bytes and said corresponding status bits, said micro-instructions causing exceptions to be taken by said microprocessor when said fetch-exception status bits indicate a fetch-exception condition.   
     
     
       2. A circuit that detects and handles fetch-exceptions for a microprocessor as defined in claim 1, further comprising a fetch address queue that temporarily stores a fetch-address when said microprocessor cannot immediately perform a requested fetch with said fetch address, and that stores fetch-exception status bits corresponding to said fetch-address, said fetch-address and said corresponding fetch-exception status bits being held until said requested fetch is performed, said fetch exception status bits being transferred to said instruction buffer when said requested fetch is performed. 
     
     
       3. A circuit that detects and handles fetch-exceptions for a microprocessor as defined in claim 1 combined with said memory, said memory being external to said microprocessor, said memory holding said instructions for said microprocessor. 
     
     
       4. A circuit that detects and handles operand-exceptions for a microprocessor without slowing down the normal operation of said microprocessor, comprising: an exception circuit that monitors operand-addresses generated by an execution unit of said microprocessor, and that performs operand-exception checks on said operand-addresses before said operand-addresses are used by said microprocessor to perform operand-accesses to memory, said exception circuit generating an exception signal on an exception signal line, said exception signal indicating detected exceptions; and   an instruction control unit that receives and decodes instructions and that generates micro-instructions based on said instructions, said instruction control unit comprising decode logic for generating a first micro-instruction for an instruction, said decode logic receiving said exception signal line from said exception circuit, said decode logic modifying a decode of said instruction when said exception signal on said exception signal line is active, said modified decode producing a micro-instruction to abort execution of said instruction and to cause a micro-interrupt.   
     
     
       5. A circuit that detects and handles operand-exceptions for a microprocessor as defined in claim 4, wherein said exception circuit detects breakpoint operand-exceptions. 
     
     
       6. A circuit that detects and handles operand-exceptions for a microprocessor as defined in claim 4, wherein said decode logic modifies said decode to cause said micro-interrupt on a same clock cycle that said operand-exception is detected. 
     
     
       7. A circuit that detects and handles operand-exceptions for a microprocessor as defined in claim 4, wherein said exception circuit further generates and maintains one or more operand-exception status bits indicating a type of operand-exception detected. 
     
     
       8. A circuit that detects and handles operand-exceptions for a microprocessor as defined in claim 4 combined with said memory, said memory being external to said microprocessor. 
     
     
       9. A method of testing for and processing address exceptions when an instruction is read into a microprocessor from a memory, said microprocessor comprising an instruction queue that simultaneously holds multiple instructions prior to execution of said instructions by said microprocessor, the method comprising the steps of: (a) testing a fetch address and generating a fetch-exception status value therefrom, said fetch address corresponding to a location in said memory of an instruction being read into said instruction queue, said fetch-exception status value indicating whether an address exception condition is detected from said address;   (b) storing said fetch-exception status value in said instruction queue in association with said instruction; and   (c) reading said fetch-exception status value from said instruction queue and decoding said fetch-exception status value to determine whether an exception should be taken.   
     
     
       10. The method according to claim 9, wherein step (c) is performed only if said instruction is read from said instruction queue for execution. 
     
     
       11. The method according to claim 9, wherein said step of decoding said fetch-exception status value is performed concurrently with a decode of said instruction. 
     
     
       12. The method according to claim 9, wherein said fetch-exception status value indicates whether a breakpoint address exception condition is detected. 
     
     
       13. The method according to claim 12, wherein said steps (a), (b) and (c) are performed while said microprocessor is operating at normal execution rates. 
     
     
       14. The method according to claim 9, wherein said fetch-exception status value is a multi-bit value which indicates the outcome of multiple address exception tests. 
     
     
       15. The method according to claim 14, wherein said multiple address exception tests include a breakpoint test, a limit error test and a page fault test. 
     
     
       16. The method according to claim 9, further comprising the step of: (d) taking an exception if said fetch-exception status value indicates that an exception condition was detected in said step (a).   
     
     
       17. The method according to claim 16, wherein said step of taking an exception is performed immediately prior to the execution of said instruction. 
     
     
       18. The method according to claim 9, further comprising the step of: (d) deleting said fetch-exception status value from said instruction queue if a program branch occurs which prevents said instruction from being executed, to thereby prevent any address exception detected in step (a) from being taken.   
     
     
       19. The method according to claim 9, wherein said step of testing said fetch address is performed before said microprocessor reads said instruction from said memory.