Data-array processing system wherein parallel processors access to the memory system is optimized

Abstract

A data array processing system comprises a memory system for storing an array of data elements and addressable by a single address, a plural number N of processors (PROC(0)-(15)) capable of processing data elements in parallel, and an address bus. In order to allow parallel access to the memory system where possible, but permit the processors also to access different addresses, each processor is selectable to supply its respective required address (xq, yq) via the address bus to the memory system to access the memory, and each non-selected processor is operable to determine whether it requires access to the address (xq, yq) on the bus, and if so to access the memory system at the same time as the selected processor.

We claim: 
     
       1. A data-array processing system, comprising: a memory system (700,740) for storing an array of data elements and addressable (on 319) by a single address (xq,yq);   a plural number N of processors (606(0)-(15); PROC(0)-(15)) capable of processing data elements in parallel and operable to read data elements from and/or write data elements to the memory system at addresses which can be the same or different for the different processors; and   an address bus (323);   wherein each processor (PROC(q)) is selectable (steps 630 to 640) to supply (step 645) its respective required address (xq,yq) via the address bus to the memory system to access (step 652) the memory system; and   wherein each non-selected processor is operable to determine (steps 646,648) whether it requires access to the address (xq,yq) on the bus and if so to access (step 652) the memory system at the same time as the processor (PROC(q)) which supplied the address to the bus.   
     
     
       2. A system as claimed in claim 1, further comprising a controller (614) operable to control an access operation; and in which the controller and processors are programmed such that: (a) the controller enables access to the memory system by a selected one (PROC(q))of the processors which requires access (steps 630-640);   (b) in response to step "a", the selected processor supplies its required address (xq,yq) to the bus (steps 645);   (c) any non-selected processor which requires access to the memory system compares the address on the bus with its required address (steps 646, 648) and if there is a match also accesses the memory (step 652); and   (d) the controller determines whether any processor still requires access to the memory (steps 630-636), and if so causes steps "a" to "d" to be repeated.   
     
     
       3. A system as claimed in claim 2, wherein prior to step "a" each processor which requires access to the memory system sets a respective "unsatisfied" flag (US) of the controller (steps 620-625), and wherein any processor which accesses the memory system resets its unsatisfied flag of the controller (step 650). 
     
     
       4. A system as described in claim 2, wherein each processor is operable to access a series of addresses, wherein prior to step "a" each processor which requires access to the memory system sets a respective "unsatisfied" flag (US) of the controller (steps 620-625), and wherein any processor which accesses the memory system maintains its unsatisfied flag set if it requires access to a further address in its series (steps 684, 688-692), or resets its unsatisfied flag if it has completed access to its series of addresses (steps 684, 686). 
     
     
       5. A system as claimed in claim 2, wherein each processor is operable to access a series of addresses, wherein each processor is operable to maintain a pointer indicative of the progress of accesses through its series of addresses; and wherein the controller is operable to give priority access to one of the processors which has progressed less through its series than another of the processors. 
     
     
       6. A system as claimed in claim 5, wherein the memory system is addressable sequentially by first and second address components (x,y), and wherein any non-selected processor which requires access to the memory at an address having a first component (x) but not a second component (y) matching the first and second components (xq,yq) of the address on the bus is given priority in a subsequent memory access over a processor which requires access to the memory system at an address having neither a first component nor a second component matching those of the address on the bus. 
     
     
       7. A system as claimed in claim 6, wherein any processor having its second address component (y) matching is given a higher priority in a subsequent memory access than any processor which has progressed least through its series of addresses. 
     
     
       8. A system as claimed in claim 2, wherein the memory system is addressable sequentially by first and second address components (x,y), and wherein any non-selected processor which requires access to the memory at an address having a first component (x) but not a second component (y) matching the first and second components (xq,yq) of the address on the bus is given priority in a subsequent memory access over a processor which requires access to the memory system at an address having neither a first component nor a second component matching those of the address on the bus. 
     
     
       9. A system as claimed in claim 8, wherein in step "c" if there is match between the first component (y) of any non-selected processor's required address and the first component (yq) of the address on the bus (steps 646, 648), that non-selected processor sets a respective "part-satisfied" flag (XW) (step 654) of the controller, and wherein in a subsequent step "a" the controller gives priority of selection to an unsatisfied processor which has set its part-satisfied flag (step 630, 632) over an unsatisfied processor which has not set its part-satisfied flag. 
     
     
       10. A system as claimed in claim 1, wherein the memory system is addressable sequentially by first and second address components (x,y), and wherein any non-selected processor which requires access to the memory at an address having a first component (x) but not a second component (y) matching the first and second components (xq,yq) of the address on the bus is given priority in a subsequent memory access over a processor which requires access to the memory system at an address having neither a first component nor a second component matching those of the address on the bus. 
     
     
       11. A system as claimed in claim 1, further comprising a sequencer (329) for controlling the sequencing of processing steps by all of the processors, the controller (614) being operable to supply a sequence enable signal (SE) to the sequencer when all of the processors have become satisfied (steps 636, 638). 
     
     
       12. A system as claimed in claim 1, wherein the memory system is operable to provide parallel access to a group of N memory locations for a group of N data elements upon addressing by a single address, and wherein some or all of the processors when accessing the same address can access different memory locations in the accessed group.