Arithmetic-free digital interpolation filter architecture

Abstract

A low precision Finite Impulse Response filter (FIR) is provided for filtering in a digital interpolation operation. The interpolation operation is comprised of two steps, a sampling rate conversion operation for interspersing zeroes between samples in an input sequence and a filtering step of filtering out images that result from this operation. The filtering operation utilizes a FIR filter that utilizes a low precision set of filter coefficients that are selected to tune the frequency response such that the low end frequency response including the pass band, the transition band, and the portion of the stop band immediately after the transition band provides a response equivalent to that commensurate with substantially higher precision FIR filter coefficients. A second, low pass filter section is provided for filtering the high frequency image energy at the output of the FIR filter to provide an overall filter response commensurate to that utilizing substantially higher precision FIR coefficients. The FIR filter coefficients utilized are restricted to the set of {-1, 0, +1} such that an arithmetic-free realization is provided wherein data is stored in a random access memory (68), with the non-zero coefficients for any interpolator output limited to a predetermined number. This predetermined number equals the maximum clock rate divided by the output sampling frequency. For each interpolator output, addresses of the associated data are stored in a ROM (72), which is operable to sequentially generate the addresses for accessing of data from a RAM (68). The sign is then changed, depending upon a sign change bit in the ROM (72), and then accumulated in an output accumulator (82). After all data is accessed from the RAM (68) for a given interpolator output, the accumulator (82) provides this output to the delta-sigma converter.

What is claimed is: 
     
       1. A digital filter for filtering a digital input signal at a sampling frequency comprised of a sequence of digital input values and providing a digital filter output signal comprised of a plurality of digital outputs, one for each of the digital input values, comprising: a first memory device for storing a portion of the sequence of digital input values;   a second memory device for storing filter coefficients associated with a Finite Impulse Response (FIR) filter function, said filter coefficients restricted to only discrete values, each of the digital outputs requiring a predetermined number of arithmetic operations to be performed between predetermined ones of the digital input values and predetermined ones of said filter coefficients stored in said second memory device, of which at least one of said arithmetic operations for each of the digital outputs results in a zero value;   an operational device for performing for each of the digital outputs each of said associated arithmetic operations with the exception of said associated at least one arithmetic operation; and   an accumulator for accumulating the results of all of said arithmetic operations performed by said operational device for each of the digital outputs and outputting the resulting digital output after accumulation of all of said associated performed arithmetic operations.   
     
     
       2. The digital filter of claim 1, wherein said filter coefficients include a plurality of zero filter coefficients. 
     
     
       3. The digital filter of claim 2, wherein said at least one arithmetic operation which results in a zero value, is one of said arithmetic operations associated with said zero filter coefficients. 
     
     
       4. The digital filter of claim 2, wherein a defined number of said predetermined number of said arithmetic operations are associated with zero value filter coefficients and said operational device is operable to perform only the ones of said arithmetic operations not including said defined number of said predetermined number of arithmetic operations. 
     
     
       5. The digital filter of claim 4, wherein said operational device is operable to sequentially perform said arithmetic operations. 
     
     
       6. The digital filter of claim 1, wherein non-zero filter coefficients are restricted to either a "-1" or a "+1" value, and wherein said operational device is operable to change the sign of the associated stored sample from said first memory device when said associated filter coefficient is a "-1" value for input to said accumulator and said operational device is operable to directly input the associated sample from said first memory device to said accumulator when said associated filter coefficient is a "+1" value. 
     
     
       7. The digital filter of claim 1, wherein said first memory device comprises a random access memory having a plurality of storage locations that are addressable by an external address, and wherein: said second memory device comprises an address/command memory having a plurality of storage locations associated therewith for storing a sequence of addresses for said random access memory for each of the digital outputs and, in association with each of said addresses, an arithmetic command representing the arithmetic operation to be performed in accordance with an associated one of said filter coefficients;   said operational device comprising an arithmetic device for receiving the output of said random access memory when addressing an output therefrom for performing an arithmetic operation indicated by said arithmetic command; and   said operational device operable to sequence said address/command memory to output said addresses and said associated arithmetic commands in order to select one of the stored samples in said random access memory for input to said arithmetic device and perform the operation of said associated arithmetic command and output the result of said arithmetic device to said accumulator for accumulation thereof during the sequencing of the addresses stored in said address/command memory for a given one of the digital outputs.   
     
     
       8. The digital filter of claim 7, wherein said filter coefficients are restricted to the set {-1, 0, +1} and said arithmetic device is operable to change the sign of said addressed sample from said random access memory when said associated filter coefficient is a "-1" value for input to said accumulator and directly input said addressed sample to said accumulator when said associated filter coefficient is a "+1" value and input a "0" value to said accumulator when said assosiated filter coefficient is a "0" value. 
     
     
       9. The digital filter of claim 7, wherein a defined number of said predetermined number of arithmetic operations for each of the digital outputs are associated with zero filter coefficients, with the sequence of addresses for each of the digital outputs stored in said address/command memory being those associated with the ones of said predetermined number of arithmetic operations not including said defined ones of said predetermined number of arithmetic operations, such that the number of arithmetic operations performed by said arithmetic devices is reduced by a defined number of arithmetic operations. 
     
     
       10. The digital filter of claim 1, and further comprising an output filter for filtering the output of said accumulator, said output filter having a low pass filter function. 
     
     
       11. The digital filter of claim 10, wherein said low-pass filter has a predetermined pass-band droop and said filter coefficients associated with said FIR filter function compensate for said pass-band droop. 
     
     
       12. The digital filter of claim 10, wherein said low pass filter has a predetermined phase response and said filter coefficients associated with said FIR filter functions compensate for said phase response. 
     
     
       13. The digital filter of claim 10, wherein said accumulator comprises a portion of said low-pass filter function. 
     
     
       14. The digital filter of claim 1, and further comprising an interpolation device for interpolating the sequence of digital values to a higher sampling frequency. 
     
     
       15. The digital filter of claim 14, wherein said interpolation device is operable to intersperse zero values between the values in the sequence of digital input values prior to filtering thereof and said operational device is operable to exclude the arithmetic operations associated with said interspersed zero values. 
     
     
       16. A digital interpolation filter for filtering a digital input signal at a first sampling frequency comprised of a sequence of digital values and providing a filtered digital output for each of the digital values, comprising: a random access memory having a plurality of storage locations for storing the digital values of the digital input signal, each of said storage locations randomly addressable by an external address for output from said random access memory;   a first memory device for storing a plurality of sequences of filter coefficients as filter coefficient sequences, each of said filter coefficient sequences associated with one of the digital outputs and each comprising the filter coefficients of a finite impulse response (FIR) filter function necessary to calculate the associated digital output;   a second memory device for storing a plurality of sequences of addresses for said random access memory as address sequences, each of said address sequences associated with one of said filter coefficient sequences in said first memory device and each of said addresses in each of said address sequences being associated with the corresponding one of said filter coefficients in the corresponding one of said filter coefficient sequences in said first memory device;   an arithmetic device for multiplying the addressed output of said random access memory with the value represented by the output of said first memory device;   an accumulator for accumulating the output of said arithmetic device; and   a control device for controlling said second memory device to sequence through the addresses in each of said address sequences in a sequential manner for addressing of said random access memory and to sequentially output from said random access memory the associated one of said stored samples to said arithmetic device, said control device controlling said first memory device to output to said arithmetic device the one of said filter coefficients corresponding to the output one of said addresses from said second memory device, the output of said accumulator at the end of each of said sequences comprising the digital output for the associated input digital value.   
     
     
       17. The digital filter of claim 16, wherein said filter coefficients are restricted to the set of {+1, 0, -1} and said arithmetic device is operable to change the sign of the output sample from said random access memory whenever the output one of said filter coefficients is a "-1" value, to directly input the output of said random access memory to said accumulator when the value of said filter coefficient is "+1" and to input a "0" value to said accumulator wherever said filter coefficient output from said first memory device is a "0" value. 
     
     
       18. The digital filter of claim 17, wherein said first memory device and said second memory device comprise a read only memory having a plurality of addressable storage locations, each of said addressable storage locations having stored therein the one of the addresses stored in said second memory device and the associated one of said filter coefficients stored in said first memory device and said control device operable to sequentially sequence through the addressable storage locations in said read only memory. 
     
     
       19. The digital filter of claim 16, wherein all of said digital outputs each have a predetermined number of arithmetic operations associated therewith and wherein a defined number of said filter coefficients are set to a "0" value for each of the digital outputs such that said address sequences only include addresses for the ones of said arithmetic operations not associated with said defined number of said filter coefficients having a "0" value. 
     
     
       20. The digital filter of claim 16, and further comprising an interpolation device for interpolating the sequence of digital values to a higher sampling frequency. 
     
     
       21. The digital filter of claim 20, wherein said interpolation device is operable to interpolate a zero value between the values in the sequence of digital values prior to filtering thereof, and said arithmetic device is operable to exclude the arithmetic operation associated with said interspersed zero values. 
     
     
       22. A processor for processing a time series of digital values, which digital values are in a predetermined sequence, comprising: an input associated with each of the digital values;   an output associated with each of the digital values to provide a processed output digital value;   a data memory for storing the input digital values;   a coefficient memory for storing a plurality of processing coefficients;   an input selection network for accessing select ones of said stored digital inputs;   a processor element for processing each of said stored digital inputs to provide an associated output in accordance with a predetermined algorithm, said predetermined algorithm requiring as data inputs a plurality of said stored input digital values including said associated digital value, and as coefficient inputs, a plurality of said stored processing coefficients, said data inputs selected by said input selection network, said predetermined algorithm having an arithmetic operation associated with each of said data inputs, with each of said arithmetic operations requiring an associated one of said input processing coefficients to provide a plurality of processed output values for each of said associated digital values; and   an accumulator for summing said processed output values for each of said outputs to provide said associated processed output digital value for each of the input digital values;   a processor controller for controlling the processing sequence in which said arithmetic operations are performed for each of said outputs and controlling said input selection network to select the appropriate one of said data inputs, wherein said processing sequence can be different than the sequence in which said associated data inputs occur in the predetermined sequence of the digital values.   
     
     
       23. The processor of claim 22, wherein each of the data inputs associated with each of the outputs is associated with one of said processor coefficients stored in said coefficient memory. 
     
     
       24. The processor of claim 22, wherein said processor coefficients include a plurality of zero processor coefficients. 
     
     
       25. The processor of claim 24, wherein each of said outputs has at least one of said associated arithmetic operations associated with one of said zero processor coefficients, and wherein said processor element is operable to perform only the ones of said arithmetic operations not including the at least one arithmetic operation. 
     
     
       26. The processor of claim 24, wherein said arithmetic operations associated with each of said outputs are the same as for others of said outputs and wherein a defined number of said arithmetic operations for each of said outputs are associated with said zero value processor coefficients and said processor element is operable to perform only the ones of said arithmetic operations not including said defined number of said arithmetic operations associated with said zero value processor coefficients. 
     
     
       27. The processor of claim 26, wherein said processor element is operable to sequentially perform said arithmetic operations for each of said outputs. 
     
     
       28. The processor of claim 22, wherein the ones of said processing coefficients having a non-zero value are restricted to either a "-1" or a "+1" value and wherein said processor element is operable to change the sign of the associated stored digital value when said associated processor coefficient is a "-1" value for input to said accumulator and said processor element is operable to directly input the associated stored digital value in said accumulator when said associated processor coefficient is a "+1" value. 
     
     
       29. The processor of claim 22, wherein said processor element operates on a predetermined number of clock cycles with each clock cycle associated with the performance of an arithmetic operation and wherein the number of non-zero coefficients is restricted to the number of clock cycles for each output to said accumulator wherein each of said outputs has a predetermined number of zero value processor coefficients associated therewith. 
     
     
       30. The processor of claim 22, and further comprising an interpolation device for interpolating the sequence of digital values to a higher sampling frequency. 
     
     
       31. The processor of claim 30, wherein said interpolation device is operable to intersperse zero values between the values of the sequence of digital values prior to processing thereof and said processor element is operable to exclude the arithmetic operation associated with said interspersed values. 
     
     
       32. The processor of claim 22, and further comprising a decimation device for selecting only predetermined ones of said outputs. 
     
     
       33. The processor of claim 32, wherein the ones of said outputs not selected by said decimation output occur on a periodic basis. 
     
     
       34. A digital filter for filtering a digital input signal at a sampling frequency comprised of a sequence of digital input values and providing a digital filter output signal comprised of a plurality of digital outputs, one for each of the digital input values, comprising: a first memory device for storing a portion of the sequence of digital input values;   a second memory device for storing filter coefficients associated with a Finite Impulse Response (FIR) filter function, said filter coefficients restricted to only discrete values, each of the digital outputs requiring a predetermined number of arithmetic operations to be performed between predetermined ones of the digital input values and predetermined ones of said filter coefficients stored in said second memory device;   a processor clock operating at a higher frequency than the sampling frequency;   an arithmetic processor for performing for each of the digital outputs each of said associated arithmetic operations, each of the arithmetic operations requiring a predetermined number of clock cycles of said processor clock with the total number of clock cycles for all of said arithmetic operation for each of the digital outputs being less than or equal to a single sampling period associated with the sampling frequency; and   an accumulator for accumulating the results of all of said arithmetic operations performed by said operational device for each of the digital outputs and outputting the resulting digital output after accumulation of all of said associated performed arithmetic operations.   
     
     
       35. The digital filter of claim 34, wherein at least one of said arithmetic operations for each of the digital outputs is a zero value and said arithmetic processor does not process said at least one of said arithmetic operations. 
     
     
       36. The digital filter of claim 35, wherein said at least one of said arithmetic operations for each of the digital outputs can be different as compared to other of the digital outputs. 
     
     
       37. A method for filtering a digital output signal at a sampling frequency is comprised of a sequence of digital input values and providing a digital filter output signal comprised of a plurality of digital outputs, one for each of the digital input values, comprising the steps of: storing a portion of the sequence of the digital input values in a first memory device;   storing filter coefficients associated with a finite impulse response (FIR) filter function in a second memory device, the filter coefficients restricted to only discrete values, each of the digital outputs requiring a predetermined number of arithmetic operations to be performed between predetermined ones of the digital input values and predetermined ones of the filter coefficients stored in the second memory device, of which at least one of the arithmetic operations for each of the digital outputs results in a zero value;   performing for each of the digital outputs each of the associated arithmetic operations with the exception of the at least one arithmetic operation; and   accumulating the results of all the arithmetic operations performed by the step of performing for each of the digital outputs and outputting the resulting digital output after accumulation of all of the associated performed arithmetic operations.   
     
     
       38. The method of claim 37, wherein the filter coefficients include a plurality of zero filter coefficients. 
     
     
       39. The method of claim 38, wherein the at least one arithmetic operation which results in a zero value is one of the arithmetic operations associated with the zero filter coefficients. 
     
     
       40. The method of claim 38, wherein a defined number of the predetermined arithmetic operations are associated with zero value filter coefficients and the step of performing is operable to perform only the ones of the arithmetic operations not including the defined number of predetermined arithmetic operations. 
     
     
       41. The method of claim 40, wherein the step of performing is operable to sequentially perform the arithmetic operations. 
     
     
       42. The method of claim 37, wherein non-zero filter coefficients are restricted to either a "-1" or a "+1" value, and wherein the step of performing is operable to change the sign of the associated stored input value in the first memory device when the associated filter coefficient is a "-1" value for use in the step of accumulating and the step of performing is operable to directly input the associated input value from the first memory device for use in the step of accumulating when the associated filter coefficient is a "+1" value. 
     
     
       43. The method of claim 37, wherein the step of storing a portion of the sequence of digital input values in the first memory device comprises storing a portion of the sequence of digital input values in a random access memory having a plurality of storage locations that are addressable by an external address, and wherein: the second memory device comprises an address/command memory having a plurality of storage locations associated therewith for storing a sequence of addresses for the random access memory for each of the digital outputs, and in association with each of the addresses, an arithmetic command representing the arithmetic operation to perform in accordance with an associated one of the filter coefficients;   the step of performing further providing the step of receiving the output of the random access memory and addressing an output therefrom and performing an arithmetic operation thereon indicated by the arithmetic command; and   the step of performing operable to sequence the address/command memory to output the addresses and the associated arithmetic commands in order to select one of the stored samples in the random access memory for use in the step of performing the operation of the associated arithmetic command and then outputting the result of the operation of the associated arithmetic command for use in the step of accumulating during the sequencing of the addresses stored in the address/command memory for a given digital output.   
     
     
       44. The method of claim 43, wherein the filter coefficients are restricted to the set {-1, 0, +1} and the step of performing the operation of the associated arithmetic command is operable to change the sign of the addressed sample from the random access memory when the associated filter coefficient is a "+1" value for use in the step of accumulating and directly utilizing the addressed sample for use in the step of accumulating when the associated filter coefficient is a "+1" value and utilizing a "0" value in the step of accumulating when the associated filter coefficient is a "0" value. 
     
     
       45. The method of claim 43, wherein a defined number of the predetermined number of arithmetic operations for each of the digital outputs is associated with a zero coefficient, with the sequence of addresses for each of the digital outputs stored in the address/command memory and those associated with the ones of the predetermined number of arithmetic operations not including the defined ones of the predetermined number of arithmetic operations, such that the number of arithmetic operations performed by the step of performing is reduced by a defined number of arithmetic operations. 
     
     
       46. The method of claim 37, and further comprising the step of filtering the output from the step of accumulation, the step of filtering utilizing a low-pass filter function. 
     
     
       47. The method of claim 46, wherein the step of filtering comprises processing the digital output signal with a low-pass filter that has a predetermined pass-band droop and the filter coefficients associated with the FIR filter function compensate for the pass-band droop. 
     
     
       48. The method of claim 46, wherein the step of filtering comprises in part the step of accumulating. 
     
     
       49. The method of claim 46, and further comprising interpolating the sequence of digital values to a higher sampling frequency. 
     
     
       50. The method of claim 49, wherein the step of interpolating is operable to intersperse zero values between the values in the sequence of digital input values prior to filtering thereof and the step of performing is operable to exclude the arithmetic operations associated with the interspersed zero values. 
     
     
       51. A method for filtering a digital input signal at a sampling frequency comprised of a sequence of digital values and providing a filtered digital output for each of the digital values, comprising the steps of: providing a random access memory having a plurality of storage locations and storing the digital values of the digital input signals in the storage locations, each of the storage locations randomly addressable by an external address for output from the random access memory;   storing a plurality of sequences of filter coefficients in a first memory device as filter coefficient sequences, each of the filter coefficient sequences associated with one of the digital outputs and each comprising the filter coefficient of a finite impulse response (FIR) filter function necessary to calculate the associated digital output;   storing a plurality of sequences of addresses for the random access memory as address sequences in a second memory device, each of the address sequences associated with one of the filter coefficient sequences in the first memory device and each of the addresses in each of the address sequences being associated with the corresponding ones of the filter coefficients in the corresponding ones of the filter coefficient sequences in the first memory device;   multiplying the addressed output of the random access memory with a value represented by the output of the first memory device in an arithmetic device;   accumulating the output of the arithmetic device in an accumulator; and   controlling the second memory device to sequence through the addresses in each of the address sequences in a sequential manner for addressing of the random access memory and to sequentially output from the random access memory and to sequentially output from the random access memory the associated one of the stored samples to the arithmetic device, the step of controlling the first memory device operable to control the first memory device to output to the arithmetic device the one of the filter coefficients corresponding to the output one of the addresses from the second memory device, the output of the accumulator at the end of each of the sequences comprising the digital output for the associated input value.   
     
     
       52. The method of claim 51, wherein the filter coefficients are restricted to the step of {+1, 0, -1} and the step of multiplying with the arithmetic device is operable to change the sign of the output sample from the random access memory whenever the output one of the filter coefficients is a "-1" value, to directly input the output of the random access memory to the accumulator when the value of the filter coefficient is "+1" and to input the "0" value to the accumulator whenever the filter coefficient output from the first memory device is a "0" value. 
     
     
       53. The method of claim 52, wherein the first memory device and the second memory device comprise a Read Only Memory having a plurality of addressable storage locations, each of the addressable storage locations having stored therein the one of the addresses stored in the second memory device and the associated one of the filter coefficients stored in the first memory device, and the step of controlling operable to sequentially sequence through the addressable storage locations in the Read Only Memory. 
     
     
       54. The method of claim 51, wherein all of the digital outputs each have a predetermined number of arithmetic operations associated therewith and wherein a defined number of the filter coefficients are set to a "0" value for each of the digital outputs such that the address sequences only include addresses for the ones of the arithmetic operations not associated with the defined number of the filter coefficients having a "0" value. 
     
     
       55. The method of claim 51, and further comprising, interpolating the sequence of digital values to a higher sampling frequency. 
     
     
       56. The method of claim 55, wherein the step of interpolating is operable to intersperse a zero value between the values in the sequence of digital values prior to filtering thereof, and the step of multiplying operable to exclude the arithmetic operation associated with the interspersed zero value. 
     
     
       57. A method for processing a time series of digital values, which digital values are in a predetermined sequence, comprising the steps of: inputting each of the digital values on a separate input associated with each of the digital values;   providing an output associated with each of the digital values to provide a processed output digital value;   storing the input digital values in the data memory;   storing a plurality of processing coefficients in a coefficient memory;   accessing select ones of the stored digital inputs with an input selection network;   processing each of the stored digital inputs to provide an associated output in accordance with a predetermined algorithm, the predetermined algorithm requiring as data inputs a plurality of the stored input digital values including the associated digital value and, as coefficient inputs, a plurality of the stored processing coefficients, the data input selected by the data input selection network, the predetermined algorithm having an arithmetic operation associated with each of the data inputs, with each of the arithmetic operations requiring an associated one of the input processing coefficients to provide a plurality of processed output values for each of the associated digital values; and   summing the processed output values in an accumulator for each of the outputs to provide the associated processed output digital value for each of the input digital values; and   controlling the processing sequence in which the arithmetic operations are performed in the step of processing and controlling the input selection network to select the appropriate one of the data inputs, wherein the processing sequence can be different than the sequence in which the associated data inputs occur in the predetermined sequence of digital values.