Reference signal generating method and circuit for differential evaluation of the content of nonvolatile memory cells

Abstract

To reduce the supply voltage of a nonvolatile memory, a read reference signal is generated having a reference threshold value ranging between the maximum permissible threshold value for erased cells and the minimum permissible threshold value for written cells. To avoid reducing the maximum supply voltage, the characteristic of the read reference signal is composed of two portions: a first portion, ranging between the threshold value and a predetermined value, presents a slope lower than that of the characteristic of the memory cells and a second portion, as of the predetermined value of the supply voltage, presents the same slope as the characteristics of memory cells. The shifted-threshold, two-slope characteristic is achieved by means of virgin cells so biased as to see bias voltages lower than the supply voltage.

We claim: 
     
       1. A reference signal generating method for differential evaluation of the content of nonvolatile memory cells, the method comprising the steps of: generating a read reference signal having an I-V characteristic, the slope of the I-V characteristic being lower, at least in one portion, than that of the I-V characteristic of the cells of said memory, the read reference signal having a reference threshold value ranging between a maximum permissible threshold value for erased cells and a minimum permissible threshold value for written cells.   
     
     
       2. A method as claimed in claim 1 wherein said step of generating a read reference signal comprises the steps of using a virgin cell and shifting its characteristic to said reference threshold value. 
     
     
       3. A method as claimed in claim 2 wherein said step of shifting said characteristic comprises the step of generating, between two terminals of said virgin cell, a bias voltage lower than the read voltage of the cells of said nonvolatile memory. 
     
     
       4. A method as claimed in claim 1, further comprising the step of generating an erase-verify reference signal having a characteristic equal to that of an erased cell with a maximum permissible threshold.   
     
     
       5. A method as claimed in claim 1, for a memory array supplied with a supply voltage wherein said step of generating a reference signal comprises the steps of: biasing a reference cell having said reference threshold value, with a voltage related to said supply voltage;   limiting the current through said reference cell when said supply voltage presents a value ranging between said reference threshold value and a predetermined value greater than said reference threshold value, to generate a first characteristic portion with a lower slope than the characteristic of the cells of said memory; and   supplying said reference cell with a current of such a value as to generate a second characteristic portion bending with and having a higher slope than said first portion, when said supply voltage presents a value greater than said predetermined value.   
     
     
       6. A method as claimed in claim 5 wherein said second characteristic portion presents a slope equal to that of the characteristic of the cells of said memory. 
     
     
       7. A reference signal generating circuit comprising: a memory comprising a plurality of nonvolatile memory cells; and   means for generating a read reference signal having an I-V characteristic, the slope of the I-V characteristic being lower, at least in one portion, than that of the I-V characteristic of the cells of said memory, wherein the read reference signal has a reference threshold value ranging between a maximum permissible threshold value for erased cells and a minimum permissible threshold value for written cells.   
     
     
       8. A circuit as claimed in claim 7, further comprising: at least one virgin cell; and   characteristic shifting means connected to said virgin cell, for shifting the characteristic of said virgin cell to said reference threshold value.   
     
     
       9. A circuit as claimed in claim 8 wherein said characteristic shifting means comprise a voltage shifter for generating, between two terminals of said virgin cell, a bias voltage lower than the read voltage of the cells of said nonvolatile memory. 
     
     
       10. A circuit as claimed in claim 7, further comprising: verify source means for generating an erase-verify reference signal having a characteristic equal to that of an erased cell with a maximum permissible threshold.   
     
     
       11. A circuit as claimed in claim 7, for a memory array supplied with a supply voltage; said circuit comprising: a first reference cell having said reference threshold value; and   means for biasing said reference cell with a bias voltage related to said supply voltage wherein the means for biasing said reference cell comprises current limiting means for limiting the current through said first reference cell, when said supply voltage presents a value ranging between said reference threshold value and a predetermined value greater than said reference threshold value, according to a first characteristic portion having a lower slope than the characteristic of the cells of said memory, and current source means supplying said first reference cell so that the current in said reference cell follows a second characteristic portion bending with and having a higher slope than said first portion, when said supply voltage presents a value greater than said predetermined value.   
     
     
       12. A circuit as claimed in claim 11 wherein said first reference cell is a virgin cell, and wherein said biasing means comprise a voltage shifter connected between a supply line (16) and a control terminal of said first reference cell, for generating for said control terminal a first bias voltage lower than said supply voltage. 
     
     
       13. A circuit as claimed in claim 12 wherein said current source means comprises a first load circuit connected between said supply line and said reference cell, wherein the circuit further comprises means for enabling said load circuit when said supply voltage is greater than said predetermined value and wherein said current limiting means comprise a second load circuit connected parallel to and presenting a higher resistance with respect to said first load circuit. 
     
     
       14. A circuit as claimed in claim 13 wherein said second load circuit comprises a first MOS transistor having a first width/length ratio, and said first load circuit comprises a second MOS transistor having a second width/length ratio smaller than said first ratio. 
     
     
       15. A circuit as claimed in claim 13 wherein said enabling means comprises a second virgin reference cell having a control terminal; and a second voltage shifter connected between said supply line and said control terminal of said second reference cell, for generating a second bias voltage for said control terminal of said second reference cell, said second bias voltage being lower than said supply voltage and said first bias voltage. 
     
     
       16. A circuit as claimed in claim 13, further comprising: a third load circuit connected parallel to said first and second load circuits and of the same resistance as said first load means;   first enabling means connected to said first and second load circuits, for enabling said first and second load circuits in memory read mode; and   second enabling means connected to said third load circuit, for enabling said third load circuit in erase-verify mode.   
     
     
       17. A method of generating a reference signal for evaluating contents of non-volatile memory cells, the method comprising the steps of: generating a read reference signal having a read reference I-V characteristic, the read reference I-V characteristic including a first portion having a positive slope, the first portion having a lower slope than the slope of an I-V characteristic of the memory cells; and   providing a reference threshold value for the read reference signal between a maximum permissible threshold value for erased memory cells and a minimum permissible threshold value for written memory cells.   
     
     
       18. The method according to claim 17 further comprising the step of generating an erase-verify reference signal having a substantially similar I-V characteristic as an I-V characteristic of an erased memory cell with a maximum permissible threshold. 
     
     
       19. The method according to claim 17 wherein the read reference I-V characteristic includes a second portion, and the step of generating a read reference signal includes the step of generating the second portion of the read reference I-V characteristic of the read reference signal, the second portion extending from the first portion and having a higher slope than the slope of the first portion. 
     
     
       20. A reference signal generating circuit comprising: a plurality of non-volatile memory cells for writing and erasing information stored therein; and   a generator for generating a read reference signal to evaluate information contents of the memory cells, the read reference signal having a read reference I-V characteristic, the read reference I-V characteristic including a first portion having a positive slope, the first portion having a lower slope than the slope of an I-V characteristic of the memory cells, the read reference I-V characteristic also having a reference threshold value between a maximum permissible threshold value for erased memory cells and a minimum permissible threshold value for written memory cells.   
     
     
       21. The circuit according to claim 20 further comprising a second generator for generating an erase-verify reference signal having a substantially similar I-V characteristic as an I-V characteristic of an erased memory cell with a maximum permissible threshold. 
     
     
       22. The circuit according to claim 20 wherein the read reference I-V characteristic includes a second portion, and the generator generates the second portion of the read I-V reference characteristic of the read reference signal, the second portion extending from the first portion and having a higher slope than the slope of the first portion.