Method fabricating an integrated circuit

Abstract

A method is provided for forming a planar surface of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A gate oxide layer is formed over a silicon substrate. A first polysilicon layer is formed over the gate oxide layer and a nitride layer is formed over the first polysilicon layer. The first polysilicon and nitride layers are then patterned and etched to form an opening which exposes a portion of the gate oxide layer. An oxidation step is then performed to form a field oxide region in the opening. The field oxide region is formed to a thickness having an upper surface substantially planar with an upper surface of the first polysilicon layer. The nitride layer is then removed and the gate oxide and first polysilicon layers are patterned and etched to form a gate electrode and an interconnect. A silicide or other conductive layer, such as a second polysilicon layer, may be formed over the remaining first polysilicon regions and a portion of the field oxide layer to connect the gate and interconnect since the upper surface of the first polysilicon layer is substantially planar with the upper surface of the field oxide region and does not cross over the field oxide region.

What is claimed is: 
     
       1. A method of forming a semiconductor integrated circuit; comprising the steps of: forming a gate oxide layer over a silicon substrate;   forming a first polysilicon layer over the gate oxide;   forming a first nitride layer over the first polysilicon layer;   patterning and etching the first nitride and first polysilicon layers to form an opening therethrough exposing a portion of the gate oxide layer;   growing a field oxide region in the opening and in a portion of the silicon substrate in the opening to a thickness wherein a central portion of the upper surface of the field oxide region is substantially planar with an upper surface of the first polysilicon layer;   removing the first nitride layer; and   patterning and etching the first polysilicon layer and gate oxide layer to form a gate electrode and interconnect wherein the gate electrode and interconnect's upper surface remains substantially planar with the central portion of the upper surface of the field oxide region.   
     
     
       2. The method of claim 1, further comprising the step of: removing the gate oxide layer in the opening before the field oxide region is formed.   
     
     
       3. The method of claim 1, wherein during the formation of the field oxide region, traces of nitride are formed along a field oxide/substrate interface and wherein the traces of nitride remain along the interface under the interconnect after the gate and interconnect are formed. 
     
     
       4. The method of claim 1, further comprising the step of: doping an upper surface of the silicon substrate in the opening with a dopant to form a channel stop before the field oxide region is formed.   
     
     
       5. The method of claim 4, wherein the dopant comprises a P-type dopant. 
     
     
       6. The method of claim 4, wherein the P-type dopant comprises boron. 
     
     
       7. The method of claim 1, further comprising the step of: depositing an N-type dopant into the first polysilicon layer.   
     
     
       8. The method of claim 7, wherein the N-type dopant comprises phosphorous. 
     
     
       9. The method of claim 1, further comprising the step of: depositing a P-type dopant into first selected regions of the silicon substrate to adjust the conductivity of the first selected regions.   
     
     
       10. The method of claim 9, further comprising the step of: depositing a P-type dopant into second selected regions of the silicon substrate to further adjust the conductivity of the second selected regions.   
     
     
       11. The method of claim 10, wherein the P-type dopant comprises boron. 
     
     
       12. The method of claim 1, further comprising the step of: forming a refractory metal silicide layer over the gate electrode, the interconnect and a portion of the field oxide region.   
     
     
       13. The method of claim 12, wherein the refractory metal silicide is formed from a refractory metal and silicon, and wherein the refractory metal is selected from the group consisting of titanium, tantalum, cobalt and nickel. 
     
     
       14. The method of claim 1, wherein the gate oxide layer has a thickness of between approximately 20-300 angstroms. 
     
     
       15. The method of claim 1, wherein the gate oxide layer is a composite layer comprising a second thin nitride layer over an oxide layer, and wherein the second nitride layer is formed over the oxide layer to a depth of approximately 10-200 angstroms. 
     
     
       16. The method of claim 15, wherein the gate oxide layer is a composite layer comprising a seal oxide layer disposed over the second thin nitride layer, and wherein the seal oxide layer is thermally grown over the second nitride layer to a depth of approximately 10 to 30 angstroms. 
     
     
       17. The method of claim 1, further comprising the step of: forming a nitride sidewall on at least the first polysilicon layer in the opening before the field oxide region is formed.   
     
     
       18. The method of claim 1, wherein the first polysilicon layer has a thickness of between approximately 100-2000 angstroms. 
     
     
       19. The method of claim 1, wherein the first nitride layer has a thickness of between approximately 800-3000 angstroms. 
     
     
       20. The method of claim 1, wherein the field oxide region has a thickness of between approximately 2000-7000 angstroms. 
     
     
       21. The method of claim 1, further comprising the step of: forming a second polysilicon layer over the first polysilicon layer before the gate electrode and interconnect are etched wherein the second polysilicon layer is disposed over a portion of the field oxide region.   
     
     
       22. The method of claim 21, further comprising the step of: forming a silicide layer over the second polysilicon layer.   
     
     
       23. The method of claim 1, wherein the field oxide is formed by wet thermal oxidation. 
     
     
       24. The method of claim 1, wherein the field oxide is formed by dry oxidation. 
     
     
       25. The method of claim 24, wherein the dry oxidation is performed at greater than atmospheric pressure. 
     
     
       26. A method of forming a semiconductor integrated circuit; comprising the steps of: forming a gate oxide layer over a silicon substrate wherein the gate oxide layer is a composite layer comprising a first nitride covering layer over an oxide layer, and wherein the first nitride covering layer is formed over the oxide layer to a depth of approximately 10-200 angstroms;   forming a polysilicon layer over the gate oxide;   forming a second nitride layer over the polysilicon layer;   patterning and etching the second nitride and polysilicon layers to form an opening therethrough exposing a portion of the gate oxide layer;   forming a field oxide region in the opening and in a portion of the silicon substrate in the opening to a depth wherein an upper surface of the field oxide region is substantially planar with an upper surface of the polysilicon layer;   removing the second nitride layer; and   patterning and etching the polysilicon layer and gate oxide layer to form a gate electrode and interconnect wherein the gate electrode and interconnect's upper surface remains substantially planar with the upper surface of the field oxide region.   
     
     
       27. The method of claim 26, wherein the gate oxide layer is a composite layer comprising a seal oxide layer disposed over the first nitride covering layer, and wherein the seal oxide layer is thermally grown over the first nitride layer to a depth of approximately 10 to 30 angstroms. 
     
     
       28. A method of forming a semiconductor integrated circuit; comprising the steps of: forming a gate oxide layer over a silicon substrate wherein the gate oxide layer is a composite layer comprising a first nitride covering layer over an oxide layer, and wherein the first nitride covering layer is formed over the oxide layer to a depth of approximately 10-200 angstroms;   forming a polysilicon layer over the gate oxide;   forming a second nitride layer over the polysilicon layer;   patterning and etching the second nitride and polysilicon layers to form an opening therethrough exposing a portion of the gate oxide layer;   forming a nitride sidewall on at least the polysilicon layer in the opening;   forming a field oxide region in the opening and in a portion of the silicon substrate in the opening to a depth wherein an upper surface of the field oxide region is substantially planar with an upper surface of the polysilicon layer;   removing the second nitride layer; and   patterning and etching the polysilicon layer and gate oxide layer to form a gate electrode and interconnect wherein the gate electrode and interconnect's upper surface remains substantially planar with the upper surface of the field oxide region.