MOS gate controlled thyristor

Abstract

On one major surface of an n - -type semiconductor substrate, a p-type base region is formed in a semiconductor substrate, and an n-type emitter region is formed in the p-type base region. A p-type source region is formed near the p-type base region. A cathode electrode has a so-called shorted emitter structure in which the cathode electrode is connected to the p-type source region, the p-type base region, and the n-type emitter region. The p-type source region preferably has a pattern adjacent the p-type base region. The p-type base region is preferably constituted by a plurality of diffusion layers which are electrically connected to each other. Therefore, turn-off characteristics of a device can be improved, and turn-on characteristics are improved without degrading the turn-off characteristics, thereby improving trade-off between the turn-on characteristics and the turn-off characteristics.

What is claimed is: 
     
       1. A semiconductor device comprising: a semiconductor substrate of a first conductivity type; a first semiconductor region of a second conductivity type formed on a first major surface of said semiconductor substrate; a second semiconductor region of the first conductivity type formed in said first semiconductor region; a third semiconductor region of the second conductivity type formed on a second major surface of said semiconductor substrate; a fourth semiconductor region of the second conductivity type formed on the first major surface of said semiconductor substrate to surround at least said first semiconductor region; a gate electrode formed on said semiconductor substrate, said first semiconductor region, and said fourth semiconductor region through an insulating film; a first electrode formed to be in contact with said second and fourth semiconductor regions; and a second electrode formed to be in contact with said third semiconductor region. 
     
     
       2. The device according to claim 1, wherein said first electrode is also formed to be in contact with said first semiconductor region. 
     
     
       3. The device according to claim 1, further comprising a fifth semiconductor region of the second conductivity type formed to be in contact with said first semiconductor region and having an impurity concentration lower than that of said first semiconductor region, and wherein said gate electrode is also formed on said fifth semiconductor region through said insulating film. 
     
     
       4. The device according to claim 3, further comprising: a first contact region where said first semiconductor region and said semiconductor substrate contact each other is larger than a second contact region where said fifth semiconductor region and said semiconductor substrate contact each other.   
     
     
       5. The device according to claim 1, further comprising a buffer layer formed to be in contact with both said semiconductor substrate and said third semiconductor region. 
     
     
       6. The device according to claim 5, wherein said second electrode is formed to be in electrical contact with both said third semiconductor region and said buffer layer. 
     
     
       7. A semiconductor device comprising: a first semiconductor substrate of a first conductivity type;   a first semiconductor region of a second conductivity type constituted by a diffusion layer formed on a first major surface of said semiconductor substrate and having a predetermined depth, a portion of said diffusion layer being shallower than each of other portions of said diffusion layer and being interposed between said other portions of said diffusion layer;   a second semiconductor region of the first conductivity type formed in said first semiconductor region;   a first electrode formed to be in contact with said second semiconductor region;   a third semiconductor region of the second conductivity type formed on a second major surface of said semiconductor substrate; and   a second electrode formed to be in contact with said third semiconductor region.   
     
     
       8. The device according to claim 7, wherein said first electrode is formed to be in contact with said first semiconductor region. 
     
     
       9. The device according to claim 7, further comprising a fourth semiconductor region of the second conductivity type formed on the first major surface of said semiconductor substrate to be adjacent to said first semiconductor region and to interpose said semiconductor substrate with an adjacent fourth semiconductor region of the second conductivity type, and a gate electrode formed on said semiconductor substrate, said first semiconductor region, and said fourth semiconductor region through an insulating film, and wherein said first electrode is also formed to be in contact with said fourth semiconductor region. 
     
     
       10. The device according to claim 9, further comprising: an auxiliary emitter region of the second conductivity type formed on the first major surface of said semiconductor substrate to be adjacent to said first semiconductor region, wherein said fourth semiconductor region and said auxiliary emitter region are formed to surround at least said first semiconductor region.   
     
     
       11. The device according to claim 9, further comprising a fifth semiconductor region of the second conductivity type formed to be in contact with said first semiconductor region and having an impurity concentration lower than that of said first semiconductor region, and wherein said gate electrode is also formed on said fifth semiconductor region through said insulating film. 
     
     
       12. The device according to claim 11, further comprising: a first contact region where said first semiconductor region and said semiconductor substrate contact each other is larger than a second contact region where said fifth semiconductor region and said semiconductor substrate contact each other.   
     
     
       13. The device according to claim 7, further comprising a buffer layer formed to be in contact with both said semiconductor substrate and said third semiconductor region. 
     
     
       14. The device according to claim 13, wherein said second electrode is formed to be in electrical contact with both said third semiconductor region and said buffer layer. 
     
     
       15. The device according to claim 7, wherein a shallow portion of a diffusion layer constituting said first semiconductor region has an impurity concentration lower than that of each of other portions of said diffusion layer of said first semiconductor region. 
     
     
       16. The device according to claim 15, wherein said first electrode is in contact with said first semiconductor region at the shallow portion of said diffusion layer constituting said first semiconductor region. 
     
     
       17. A semiconductor device comprising: a semiconductor substrate of a first conductivity type;   a first semiconductor region of a second conductivity type formed on a first major surface of said semiconductor substrate;   a second semiconductor region of the first conductivity type constituted by a diffusion layer formed in said first semiconductor region and having a predetermined depth, a portion of said diffusion layer being shallower than each of other portions of said diffusion layer and being interposed between said other portions of said diffusion layer;   a first electrode formed to be in contact with said second semiconductor region;   a third semiconductor region of the second conductivity type formed on a second major surface of said semiconductor substrate;   a second electrode formed to be in contact with said third semiconductor region;   a fourth semiconductor region of the second conductivity type formed on the first major surface of said semiconductor substrate to be adjacent to said first semiconductor region and to interpose said semiconductor substrate with an adjacent fourth semiconductor region of the second conductivity type; and   a gate electrode formed on said semiconductor substrate, said first semiconductor region, and said fourth semiconductor region through an insulating film,   wherein said first electrode is formed to be in contact with said fourth semiconductor region.   
     
     
       18. The device according to claim 17, wherein a shallow portion of said diffusion layer constituting said second semiconductor region has an impurity concentration lower than that of each of other portions of said second semiconductor region. 
     
     
       19. The device according to claim 17, further comprising a fifth semiconductor region of the second conductivity type formed to be in contact with said first semiconductor region and having an impurity concentration lower than that of said first semiconductor region, wherein said gate electrode is formed on said fifth semiconductor region through said insulating film. 
     
     
       20. The device according to claim 17, further comprising: a first contact region where said first semiconductor region and said semiconductor substrate contact each other is larger than a second contact region where said fifth semiconductor region and said semiconductor substrate contact each other.   
     
     
       21. The device according to claim 17, further comprising a buffer layer formed to be in contact with both said semiconductor substrate and said third semiconductor region. 
     
     
       22. The device according to claim 21, wherein said second electrode is formed to be in electrical contact with both said third semiconductor region and said buffer layer. 
     
     
       23. A semiconductor device comprising: a semiconductor substrate of a first conductivity type;   a first semiconductor region of a second conductivity type constituted by a diffusion layer formed on a first major surface of said semiconductor substrate and having a predetermined depth, including a first portion of an end of said diffusion layer being an on-gate region and a second portion, said first portion being embedded in said second portion and shallower than a second portion of said diffusion layer;   a second semiconductor region of the first conductivity type formed in said first semiconductor region;   a first electrode formed to be in contact with said second semiconductor region;   a third semiconductor region of the second conductivity type formed on a second major surface of said semiconductor substrate;   a second electrode formed to be in contact with said third semiconductor region;   a fourth semiconductor region of the second conductivity type formed on the first major surface of said semiconductor substrate to be adjacent to said first semiconductor region and to interpose said semiconductor substrate with an adjacent fourth semiconductor region of the second conductivity type;   a gate electrode formed on said semiconductor substrate, said first semiconductor region including the shallow portion of said diffusion layer, and said fourth semiconductor region through an insulating film; and   wherein said first electrode is also formed to be in contact with said fourth semiconductor region.   
     
     
       24. The device according to claim 23, wherein the first portion of said diffusion layer of said first semiconductor region serving as said on-gate region has an impurity concentration lower than that of the second portion of said diffusion layer of said first semiconductor region. 
     
     
       25. The device according to claim 23, wherein the widths of said first semiconductor region and said second semiconductor region are gradually decreased near the shallow portion of said diffusion layer serving as said on-gate region, and the width of said first electrode formed in said second semiconductor region is gradually decreased near the shallow portion of said diffusion layer. 
     
     
       26. The device according to claim 23, further comprising a buffer layer formed to be in contact with both said semiconductor substrate and said third semiconductor region. 
     
     
       27. The device according to claim 26, wherein said second electrode is formed to be in electrical contact with both said third semiconductor region and said buffer layer. 
     
     
       28. The semiconductor device comprising: a semiconductor substrate of a first conductivity type; a first semiconductor region of a second conductivity type formed on a first major surface of said semiconductor substrate; a second semiconductor region of the first conductivity type formed in said first semiconductor region; a third semiconductor region of the second conductivity type formed on a second major surface of said semiconductor substrate; a fourth semiconductor region of the second conductivity type formed to be adjacent to said first semiconductor region and to interpose said semiconductor substrate with an adjacent fourth semiconductor region of the second conductivity type; a gate electrode formed on said semiconductor substrate, said first semiconductor region, and said fourth semiconductor region through an insulating film; a first electrode formed to be in contact with said second semiconductor region and said fourth semiconductor region; a second electrode formed to be in contact with said third semiconductor region; a first low-resistance film formed in said first semiconductor region on said fourth semiconductor region side to be in contact with only said first semiconductor region; and a second low-resistance film formed in said fourth semiconductor region on said first semiconductor region side to be in contact with both said fourth semiconductor region and said first electrode. 
     
     
       29. The device according to claim 28, wherein said first low-resistance film is buried in said first semiconductor region, and said second low-resistance film is buried in said fourth semiconductor region. 
     
     
       30. The device according to claim 28, wherein said first semiconductor region is connected to said fourth semiconductor region. 
     
     
       31. The device according to claim 28, further comprising a fifth semiconductor region of the second conductivity type formed to be in contact with said first semiconductor region and having an impurity concentration lower than that of said first semiconductor region, and wherein said gate electrode is formed on said fifth semiconductor region through said insulating film. 
     
     
       32. The device according to claim 31, further comprising: a first contact region where said first semiconductor region and said semiconductor substrate contact each other is larger than a second contact region where said fifth semiconductor region and said semiconductor substrate contact each other.   
     
     
       33. The device according to claim 28, further comprising a buffer layer formed to be in contact with both said semiconductor substrate and said third semiconductor region. 
     
     
       34. The device according to claim 33, wherein said second electrode is formed to be in electrical contact with both said third semiconductor region and said buffer layer.