SCR inductor transient clamp

Abstract

A monolithic voltage clamp provides low impedance, low voltage electrostatic discharge protection for an integrated circuit without affecting the integrated circuit's DC characteristics. First, second, third, and fourth regions of semiconducting material are formed with p-n junctions between each region. A first inductor electrically connects the first and second regions, and a second inductor electrically connects the third and fourth regions. The first and second inductors should each have an inductance which is large enough to delay an increase in bypass current around their respective p-n junctions for a period which is long enough to assure that conduction is sufficient to discharge an electrostatic pulse. In a preferred embodiment, first and second reverse bias diodes are used to electrically connect the invention to one or more input/output nodes. In another embodiment, an integrated circuit having first and second potential inputs, and a plurality of input/output nodes, may be provided with a transient clamp according to the invention. Along with the first and second reverse bias diodes used to connect the invention to one or more input/output nodes, third, fourth, fifth, and sixth reverse bias diodes may be used to electrically connect the first and second potential inputs to respective first and fourth semiconducting regions. In this configuration, an input/output node can operate at voltages above and below supply voltages provided to the first and second potential inputs, limited only by the breakdown voltages of the third and fourth reverse bias diodes.

That which is claimed: 
     
       1. A monolithic voltage clamp comprising: first, second, third, and fourth regions of semiconducting material, said first and third regions being of a first type conductivity and said second and fourth regions being of a second type conductivity, such that p-n junctions are formed between said first and second regions, said second and third regions, and said third and fourth regions;   a first inductor electrically connecting said first and second regions; and   a second inductor electrically connecting said third and fourth regions.   
     
     
       2. A voltage clamp according to claim 1 wherein said first inductor has an inductance which is large enough to delay an increase in bypass current around the p-n junction between said first and second regions for a period which is long enough to assure that conduction is sufficient to discharge an electrostatic discharge, and wherein said second inductor has an inductance which is large enough to delay an increase in bypass current around the p-n junction between said third and fourth regions for a period which is long enough to assure that conduction is sufficient to discharge an electrostatic discharge.   
     
     
       3. A voltage clamp according to claim 1 wherein said first inductor and said second inductor have inductance values between about 20 nH to 50 nH. 
     
     
       4. A voltage clamp according to claim 1 wherein one of said first and second inductors has an inductance between about 20 nH to 50 nH. 
     
     
       5. A voltage clamp according to claim 1 wherein said first and third region are of N-type conductivity and wherein said second and fourth regions are of P-type conductivity, said voltage clamp further comprising: a first diode, having an anode and a cathode, electrically connected between an I/O node and said first region, the anode of said first diode being connected to said first region and the cathode of said first diode being connected to the I/O node; and   a second diode, having an anode and a cathode, electrically connected between the I/O node and said fourth region, the anode of said second diode being connected to said I/O node and the cathode of said second diode being connected to said fourth region.   
     
     
       6. A voltage clamp according to claim 1 and further comprising: a substrate resistor electrically connected in parallel to one of said first inductor and said second inductor, the resistance of said substrate resistor being high enough to allow the voltage clamp to latch.   
     
     
       7. A voltage clamp according to claim 6 wherein said substrate resistor has a resistance value of at least about 10 ohms. 
     
     
       8. An SCR voltage clamp comprising: first, second, third, and fourth regions of semiconducting material, said first and third regions being of a first type conductivity and said second and fourth regions being of a second type conductivity, such that p-n junctions are formed between said first and second regions, said second and third regions, and said third and fourth regions;   a first inductor electrically connecting said first and second regions, said first inductor having an inductance which is large enough to delay an increase in bypass current around the p-n junction between said first and second regions for a period which is long enough to assure that conduction is sufficient to discharge an electrostatic discharge;   a second inductor electrically connecting said third and fourth regions, said second inductor having an inductance which is large enough to delay an increase in bypass current around the p-n junction between said third and fourth regions for a period which is long enough to assure that conduction is sufficient to discharge an electrostatic discharge;   a first reverse bias diode electrically connected between an I/O node and said first region;   a second reverse bias diode electrically connected between the I/O node and said fourth region;   a substrate resistor electrically connected in parallel to one of said first inductor and said second inductor, the resistance of said substrate resistor being high enough to allow the voltage clamp to latch.   
     
     
       9. A voltage clamp according to claim 8 wherein said first and third regions are of N-type conductivity and wherein said second and third regions are of P-type conductivity, and wherein said first reverse bias diode comprises a first diode, having an anode and a cathode, electrically connected between the I/O node and said first region, the anode of said first diode being connected to said first region and the cathode of said first diode being connected to the I/O node, and   wherein said second reverse bias diode comprises a second diode, having an anode and a cathode, electrically connected between said I/O node and said fourth region, the anode of said second diode being connected to the I/O node and the cathode of said second diode being connected to said fourth region.   
     
     
       10. A voltage clamp according to claim 8 wherein said first inductor and said second inductor have inductance values between about 20 nH to 50 nH. 
     
     
       11. A voltage clamp according to claim 8 wherein said substrate resistor has a resistance value of at least about 10 ohms. 
     
     
       12. An integrated circuit with an SCR transient clamp comprising: an integrated circuit having first and second potential inputs and a plurality of I/O nodes;   an SCR having first, second, third, and fourth regions of semiconducting material, said first and third regions being of a first type conductivity and said second and fourth regions being of a second type conductivity, such that p-n junctions are formed between said first and second regions, said second and third regions, and said third and fourth regions;   a first inductor electrically connecting said first and second regions, said first inductor having an inductance which is large enough to delay an increase in bypass current around the p-n junction between said first and second regions for a period which is long enough to assure that conduction is sufficient to discharge an electrostatic discharge;   a second inductor electrically connecting said third and fourth regions, said second inductor having an inductance which is large enough to delay an increase in bypass current around the p-n junction between said third and fourth regions for a period which is long enough to assure that conduction is sufficient to discharge an electrostatic discharge;   a first reverse bias diode electrically connected between at lease one I/O node and said first region;   a second reverse bias diode electrically connected between said at least one I/O node and said fourth region; and   a substrate resistor electrically connected in parallel to one of said first inductor and said second inductor, the resistance of said substrate resistor being high enough to allow the voltage clamp to latch.   
     
     
       13. A voltage clamp according to claim 12 and further comprising: a third reverse bias diode electrically connected between said first potential input and said first region;   a fourth reverse bias diode electrically connected between said first potential input and said fourth region;   a fifth reverse bias diode electrically connected between said second potential input and said first region; and   a sixth reverse bias diode electrically connected between said second potential input and said fourth region, such that said plurality of I/O nodes can operate at voltages above and below any supply voltages electrically connected to said first and second potential inputs but which are limited by breakdown voltages of said third, fourth, fifth, and sixth reverse bias diodes.   
     
     
       14. A voltage clamp according to claim 12 wherein said first inductor and said second inductor have inductance values between about 20 nH to 50 nH. 
     
     
       15. A voltage clamp according to claim 12 wherein said substrate resistor has a resistance value of at least about 10 ohms.