Process for fabricating bipolar junction transistor having reduced parasitic capacitance

Abstract

A process for fabricating a BJT device on a semiconductor substrate is disclosed. The substrate serves as the collector. The process comprises the steps of, first, forming a shielding layer over the designated location over the surface of the substrate for defining the active region. The process further utilizes the shielding layer as the shielding mask for implanting impurities of into the substrate for forming an doped region. Then, a first field oxide layer is formed over the doped region and then removed. Sidewall spacers for the shielding layer are then formed. The process then utilizes the shielding layer and the sidewall spacers as the shielding mask for implanting impurities into portions of the doped region, forming a heavily-doped region, and the remaining portion of the doped region defines the base region. A second field oxide layer is then formed over the heavily-doped region. The sidewall spacers are then removed to form trenches in the places of the sidewall spacers. The process then forms emitter electrodes in the trenches, and then implants impurities into the base region via the emitter electrodes, thereby forming the emitter regions. The fabricated BJT has reduced inherent parasitic capacitance and improved switching speed characteristics.

What is claimed is: 
     
       1. A process for fabricating a bipolar junction transistor device on a semiconductor substrate of a first conductivity type, wherein said substrate serves as a collector for said bipolar junction transistor device, comprising: forming a shielding layer with designated pattern on said substrate;   implanting impurities of a second conductivity type into said substrate to form doped regions by utilizing said shielding layer as masking;   forming a first oxide layer over said doped regions through a first thermal oxidation;   removing said first oxide layer;   forming spacers on the sidewalls of said shielding layer;   implanting impurities of the second conductivity type into said substrate to form heavily-doped regions by utilizing said shielding layer and spacers as masking;   forming a second oxide layer over said heavily-doped regions through a second oxidation;   removing said spacers to form trenches in places of said spacers;   forming emitter electrodes on said doped regions via said trenches, and forming emitter regions of the first conductivity type beneath said emitter electrodes; and   forming a contact region of the first conductivity type in said collector.   
     
     
       2. The process for fabricating said bipolar junction transistor device of claim 1, wherein the step of forming said shielding layer comprises: forming a pad oxide layer and depositing a nitride layer thereon. 
     
     
       3. The process for fabricating said bipolar junction transistor device of claim 2, wherein the step of removing said spacers further removes said nitride layer of said shielding layer. 
     
     
       4. The process for fabricating said bipolar junction transistor device of claim 1, wherein the step of forming said spacers comprises: depositing a nitride layer on overall surface; and   etching back said nitride layer to form said spacers.   
     
     
       5. The process for fabricating said bipolar junction transistor device of claim 1, wherein said emitter electrodes are made of polysilicon. 
     
     
       6. The process for fabricating said bipolar junction transistor device of claim 1 wherein said first conductivity type is N-type and said second conductivity type is P-type. 
     
     
       7. The process for fabricating said bipolar junction transistor device of claim 1 wherein said first conductivity type is P-type and said second conductivity type is N-type.