Thin-film transistor and method for forming the same

Abstract

A transistor is formed on a substrate of dielectric material. The transistor includes a layer of semiconductor material that is formed on the substrate and has a source region and a drain region. The layer also has a channel region that is in a recess of the substrate and adjacent to the source and drain regions. The channel is self-aligned, as are the light doped source and drain regions.

I claim: 
     
       1. A semiconductor structure, comprising: a dielectric substrate having a surface and having a recess formed therein, said recess having a sidewall;   a layer of semiconductor material disposed on said surface and in said recess, said layer defining a source region, a drain region, and a channel region that is entirely within said recess, is contiguous with said sidewall, and is between and contiguous with said source and drain regions;   a gate electrode disposed on said surface of said substrate and substantially outside of said recess, said gate electrode having an end portion that extends beyond said sidewall of said recess and that is adjacent to said channel region; and   an insulator layer disposed between and contiguous with said end portion of said gate electrode and said channel region.   
     
     
       2. The structure of claim 1 wherein a first portion of said source region and a first portion of said drain region are disposed within said recess, and a second portion of said source and a second portion of said drain are disposed on said surface of said substrate and outside of said recess. 
     
     
       3. The structure of claim 1 wherein said source region includes a lightly doped source region that is contiguous with said channel, and wherein said drain region includes a lightly doped drain region that is contiguous with said channel. 
     
     
       4. The structure of claim 3 wherein at least a portion of said lightly doped source region and a portion of said lightly doped drain region are disposed within said recess. 
     
     
       5. The structure of claim 1 wherein said gate electrode has a pair of opposing sides that are substantially perpendicular to said surface of said substrate and that have said insulator layer disposed thereon, wherein a portion of said source region is adjacent a first of said sides and a portion of said drain region is adjacent a second of said sides, and wherein said insulator layer separates said portion of said source region from said first side and separates said portion of said drain region from said second side. 
     
     
       6. The structure of claim 5 wherein said source region comprises a lightly doped source region that is contiguous with said channel and adjacent to said first side of said gate electrode, and wherein said drain region comprises a lightly doped drain region that is contiguous with said channel region and adjacent to said second side of said gate electrode. 
     
     
       7. The structure according to claim 5 in which said portion of said source region and said portion of said drain region respectively have a greater volume than a portion of said source region and a portion of said drain region that are spaced from said channel region to self-create a lower concentration of dopant immediately adjacent said channel region. 
     
     
       8. A method for forming a transistor, comprising: forming a gate electrode on a surface of a dielectric substrate;   forming a recess in said substrate such that said recess and said surface are contiguous at a boundary at which an end portion of said gate extends over said recess;   forming an insulator on exposed portions of said gate;   forming a layer of semiconductor material on said surface and in said recess such that said gate electrode overlays said semiconductor layer;   forming a channel region in said semiconductor material within said recess; and   forming drain and source regions in said semiconductor material adjacent opposing ends of said channel to provide said transistor.   
     
     
       9. The method of claim 8 wherein said step of forming a gate electrode comprises: depositing a film of polysilicon on said surface;   forming a mask layer over said film;   etching exposed portions of said film to form said gate electrode; and   removing said mask layer.   
     
     
       10. The method of claim 8 wherein said step of forming a recess comprises: forming after said gate electrode is formed, a mask layer that exposes said end portion of said gate electrode and an area of said substrate surface adjacent to said end portion; and   isotropically etching said exposed substrate area so as to undercut said end portion of said gate electrode.   
     
     
       11. The method of claim 8 wherein said steps of forming a layer of semiconductor material and forming a channel region together comprise: depositing a film of amorphous silicon on said surface of said substrate and in said recess;   forming a mask layer over said amorphous silicon;   anisotropically etching said silicon to leave a strip within said recess;   implanting with a dopant a portion of said strip remaining in said recess to form said channel;   removing said mask layer; and   converting said strip to polysilicon.   
     
     
       12. The method of claim 8 wherein said step of forming said semiconductor layer includes: forming a layer of silicon overlaying said gate electrode and in said recess overlaid by said gate electrode to provide some of said semiconductor layer above said gate electrode, some to the side of said gate electrode and some below said gate electrode.   
     
     
       13. The semiconductor structure of claim 1 wherein: said gate electrode has a surface that is substantially parallel to said surface of said substrate and that faces away from said recess;   a portion of said insulator layer is disposed on said surface of said gate electrode; and   a portion of said semiconductor layer is disposed on said portion of said insulator layer.   
     
     
       14. A method for forming a transistor, comprising: forming on a surface of an insulator substrate a gate electrode having an end portion that has an end-portion surface contacting said substrate surface;   after said forming a gate electrode, forming in said substrate a recess that exposes said end-portion surface;   forming an insulator layer on said exposed end-portion surface;   forming a semiconductor layer on said surface of said substrate and in said recess; and   forming in said semiconductor layer a drain and a source that are contiguous with first and second ends, respectively, of a channel.   
     
     
       15. The method of claim 14 wherein said forming a semiconductor layer comprises forming said semiconductor layer adjacent to multiple surfaces of said end portion of said gate electrode. 
     
     
       16. The method of claim 14 wherein said forming a gate electrode comprises: depositing a film of polysilicon on said surface of said substrate;   forming a mask layer over said film;   etching exposed portions of said film to form said gate electrode; and   removing said mask layer.   
     
     
       17. The method of claim 14 wherein said forming a recess comprises: forming a mask layer that exposes said end portion of said gate electrode and an area of said substrate surface that is adjacent to said end portion; and   isotropically etching said exposed area of said substrate surface to undercut said end portion of said gate electrode.   
     
     
       18. The method of claim 14 wherein said forming a semiconductor layer comprises: depositing a film of amorphous silicon on said surface of said substrate and in said recess;   forming a mask layer on said film;   anisotropically etching said film to form a strip of amorphous silicon within said recess;   implanting with a dopant a portion of said strip to form said channel;   removing said mask layer; and   converting said strip of amorphous silicon to polysilicon.   
     
     
       19. The method of claim 14, further comprising forming said channel in said semiconductor layer such that said channel is entirely within said recess and adjacent to said end-portion surface.