Voltage regulator with high gain cascode mirror

Abstract

A bandgap generator including an MOS current mirror, first and second bipolar transistors and an MOS transistor pair operating in saturation. Cascode transistors interconnect the saturation transistor pair and the MOS transistor pair. A bias resistor interconnects the one of the cascode transistors and one transistor of the MOS current mirror.

What is claimed is: 
     
       1. AMOS bandgap voltage generator coupled between a first and second voltage source, said bandgap generator comprising: first and second MOS transistors, each coupled to said first voltage source and to each other in such manner that said first and second MOS transistors form current sources, a second current from said second MOS transistor mirroring a first current from said first MOS transistor;   first and second bipolar transistors, each having a base-emitter junction and coupled to said second voltage source, said first bipolar transistor coupled to said first MOS transistor for receiving said first current therethrough, said second bipolar transistor coupled to said second MOS transistor for receiving said second current therethrough;   resistive means coupled between said first MOS transistor and said first bipolar transistor;   third and fourth MOS transistors, each having first and second source/drain terminals and a gate terminal, said third MOS+transistor having said first source/drain terminal coupled to said resistive means and said second source/drain terminal coupled to said first MOS transistor, said fourth MOS transistor having said first source/drain terminal coupled to said second bipolar transistor and said second source/drain terminal coupled to said second MOS transistor, said gate terminals of said third and fourth MOS transistors coupled in common to a first node maintaining said third and fourth MOS transistors in saturation, said first and second bipolar transistors differently sized so that a differential in base-emitter junction voltages between said first and second bipolar transistors is generated across said resistive means;   first and second cascode transistors, each having first and second source/drain terminals and a gate terminal, coupled to each other, said first cascode transistor having said first source/drain terminal coupled to said second source/drain terminal of said third MOS transistor and said second source/drain terminal coupled to said first MOS transistor, said second cascode transistor having said first source/drain terminal coupled to said second source/drain terminal of said fourth MOS transistor and said second source/drain terminal coupled to said second MOS transistor, said gate terminals of said first and second cascode transistors coupled in common to a second node maintaining said first and second cascode transistors in saturation; and   a bias resistor having first and second terminals, said first terminal coupled to said second source/drain terminal of said second cascode transistor and said second terminal coupled to said second MOS transistor, and wherein said first node comprises said second source/drain terminal of second cascode transistor and said second node comprises said second terminal of said bias resistor.   
     
     
       2. The bandgap voltage generator of claim 1 further comprising third and fourth cascode transistors, each having first and second source/drain terminals and a gate terminal, said third cascode transistor having said first source/drain terminal coupled to said first MOS transistor and said second source/drain terminal coupled to second source/drain terminal of said first cascode transistor, said fourth cascode transistor having said first source/drain terminal coupled to said second MOS transistor and said second source/drain terminal coupled to second terminal of said bias resistor, said gate terminals of said third and fourth cascode transistors coupled in common to a third node maintaining said third and fourth cascode transistors in saturation.