Semiconductor memory device capable of data transfer between memory arrays coupled to different data pins and operating method thereof

Abstract

A dual port random access memory capable of inputting/outputting data bit by bit includes a plurality of memory cell arrays (100a, 100b, 100c, 100d) accessible in parallel, a plurality of data registers (9a, 9b, 9c, 9d) arranged to be connected to memory arrays, and transfer gates (8a', 8b', 8c', 8d') for selectively connecting each of the data registers to one memory array in response to a destination designating signal. The transfer gate includes elements (T1, T2) for connecting the data registers and the memory arrays such that each of the plurality of memory arrays is connected to different data registers. Each of the data registers is capable of transferring data of one row of the memory array at one time. The data register is capable of serially inputting and outputting data. This structure enables rearrangement of data and transfer of data row by row between memory arrays in the memory device.

What is claimed is: 
     
       1. A semiconductor memory device having a plurality of data pins for receiving or supplying data bits in parallel, comprising: a plurality of memory cell arrays, each memory cell array being associated with a different data pin among said plurality of data pins and having a plurality of memory cells arranged in a matrix of rows and columns;   a plurality of register means, each register means having sufficient storage capacity to carry out exchange of data with one row of memory cells of one memory cell array; and   means provided corresponding to each of the register means for selectively coupling a corresponding register means to at least two memory cell arrays, said means for selectively coupling including means responsive to a destination memory array designating signal for selectively connecting said corresponding register means to said at least two memory cell arrays for enabling collective transfer of data of one row of one memory cell array, through said corresponding register means, to any other memory cell array of said at least two memory arrays.   
     
     
       2. A semiconductor memory device according to claim 1, wherein said semiconductor memory device is a multiport random access memory having a first port accessing said plurality of memory cell arrays at random sequence and a second port accessing said plurality of memory cell arrays only by a serial sequence;   said plurality of memory cell arrays input or output data in parallel; and   said plurality of register means are included in said second port.   
     
     
       3. A semiconductor memory device according to claim 1, further comprising: data latching means provided separate from said plurality of register means and corresponding to said each memory cell array for serially receiving and latching external data; and   means for serially reading stored data of said plurality of register means.   
     
     
       4. A semiconductor memory device according to claim 1, wherein the number of said plurality of register means is at least the same as that of said plurality of memory cell arrays, and   said means for coupling is adapted to connect said each memory cell array to said corresponding register means in one to one correspondence.   
     
     
       5. A semiconductor memory device according to claim 1, wherein said each register means is provided per two memory cell arrays, and   said means for coupling is adapted to selectively connect only one of said at least two memory cell arrays to the corresponding register means.   
     
     
       6. A multiport semiconductor memory device having a plurality of data pins associated with each port for receiving or supplying data and capable of inputting/outputting data bits by bits, each port being accessible independently from any other port, comprising: a plurality of random access memory cell arrays, each being associated with a different data pin in the same port and each having memory cells arranged in a matrix of rows and columns, said plurality of random access memory cell arrays being accessible in parallel;   a plurality of register means, each register means arranged to be able to be connected to at least two random access memory cell arrays, the number of said plurality of register means is not less than that of said plurality of random access memory cell arrays, said each register means having sufficient storage capacity to store data of one row of said each random access memory cell array;   means provided corresponding to each of said plurality of register means and responsive to a destination memory array designating signal for selectively connecting a corresponding register means to said at least two random access memory cell arrays to realize data transfer of one row of data of one random access memory cell array, through said corresponding register means, to any other random access memory cell array of said at least two memory cell arrays; and   means for serially reading stored data of said each register means through a port other than said same port;   said each register means transferring data of one row at one time with a coupled random access memory cell array and including latching means provided corresponding to each column of said each random access memory cell array for latching signal potential on a corresponding column, and means responsive to a transfer mode designating signal for enabling or disabling said latching means.