ESD protection using SCR clamping

Abstract

An SCR clamp provides a low impedance discharge path for static charges across on IC's pins. The SCR clamp cathode, cathode, gate anode, and anode gate float when the protected IC is disconnected from its associated circuit elements. Under this condition, the SCR clamp can be turned on at the low Vh and Ih levels of the SCR, allowing the clamp to operate to discharge static electricity at the low voltage determined by SCR junction biases.

I claim: 
     
       1. An ESD device for providing a discharge path for a static charge comprising: a set of floating pins;   an SCR clamp having a plurality of SCR's;   each of said plurality of SCR's having SCR terminals   each of said plurality of SCR's having separate anode, anode gate, cathode and cathode gate SCR terminals;   said SCR terminals of each of said plurality of SCR's being connected to a separate combination of said floating pins; and at least a first of said SCR's of said plurality of SCR's, is arranged to conduct in response to a potential between a pair of floating pins of said set of floating pins.   
     
     
       2. The ESD device of claim 1, wherein: said set of floating pins is connected to said plurality of SCR's anode, anode gate, cathode and cathode gate terminals in at least four separate combinations of connections.   
     
     
       3. The ESD device of claim 2, wherein: each of said four separate combinations of connections differs in at least one floating pin connection.   
     
     
       4. The ESD device of claim 1, wherein: said set of floating pins is arranged in two pairs of floating pins including a first set of floating pins and a second set of floating pins;   said plurality of SCR's is arranged in a set of four SCR's;   a first of said set of four SCR's is connected by its anode to a first pin of said first set of floating pins and cathode to a second pin of said first set of floating pins, and anode gate to a first pin of said second set of floating pins and cathode gate to a second pin of said second set of floating pins; and   a second of said set of four SCR's is connected, by its anode, to said first pin of said first set of floating pins and cathode to said second pin of said second set of floating pins, and anode gate to said first pin of said second set of floating pins and cathode gate to said second pin of said first set of floating pins; and   a third of said set of four SCR's is connected by its anode to said first pin of said second set of floating pins and by its cathode to said second pin of said first set of floating pins, and by its anode gate connected to said first pin of said first set of floating pins and by its cathode gate to said second pin of said second set of floating pins; and   a fourth of said set of four SCR's is connected by its anode to said first pin of said second set of floating pins and by its cathode to said second pin of said second set of floating pins, and by its anode gate connected to said first pin of said first set of floating pins and by its cathode gate to said second pin of said first set of floating pins.   
     
     
       5. The ESD device of claim 4, wherein: said first of said set of four SCR's is arranged to conduct, produces conductive paths in said second and third SCR's of said set of four SCR's.   
     
     
       6. The ESD device of claim 4 wherein: said cathode gate of said first of said set of four SCR's arranged to conduct provides base current to the cathode gate of said third SCR and the anode gate of said first SCR arranged to conduct provides base current to the anode gate of said second SCR; and   said second and third SCR's are arranged to conduct in response to said base current.   
     
     
       7. The ESD device of claim 1, wherein: said first of said SCR's is arranged to conduct in response to said potential producing a voltage and current levels above the holding voltage level and holding current level for said first of said SCR's.   
     
     
       8. The ESD device of claim 1, including: said set of floating pins includes a plurality of pairs of floating pins;   a first set of terminals for connection of said ESD device to provide a discharge path;   each of said first set of terminals, connected to a said pair of said floating pins and to said SCR clamp;   said SCR clamp arranged to provide a conductive path for an electrostatic charge between of said first set of terminals.   
     
     
       9. The ESD device of claim 8, including: said plurality of pairs of floating pins includes a first pair of floating pins;   a first transistor pair;   said first transistor pair is connected to a first pair of said terminals of said first set of terminals and connects said first pair of said terminals to said first and second floating pins in said first pair of floating pins.   
     
     
       10. The ESD device of claim 9 wherein: one transistor of said first transistor pair is an NPN transistor and a second transistor of said first transistor pair is a PNP transistor.   
     
     
       11. The ESD device of claim 9, including: a second transistor pair;   said second transistor pair is connected to a first set of said terminals and connects said first set of said terminals to first and second floating pins in said first pair of floating pins.   
     
     
       12. The ESD device of claim 11 including: said plurality of floating pins includes a second pair of floating pins   a third transistor pair,   a second set of terminals for connection of said ESD device to provide a discharge path;   said third transistor pair is connected to said second set of terminals and connects said second set of terminals to said first and second floating pins of said second pair of floating pins.   
     
     
       13. The ESD device of claim 12 including: a fourth transistor pair;   said fourth transistor pair is connected to said second set of terminals and connects said second set of terminals to said first and second floating pins in said second pair of floating pins.   
     
     
       14. The ESD device of claim 12 wherein: one transistor of said third transistor pair is an NPN transistor and a second transistor of said third transistor pair is a PNP transistor.   
     
     
       15. The ESD device of claim 11 wherein: one transistor of said second transistor pair is an NPN transistor and a second transistor of said second transistor pair is a PNP transistor.   
     
     
       16. The ESD device of claim 1, including: said set of floating pins includes a first pair of floating pins;   a first set of terminals having a first terminal and a second terminal for connection of said ESD device to provide a discharge path;   a first transistor pair;   a first transistor of said first transistor pair is connected by its collector to first pin of said first pair of floating pins, by its base to second pin of said first pair of floating pins, and by its emitter to said first terminal of said first set of terminals; and   a second transistor of said first transistor pair is connected by its base to said first pin of said first pair of floating pins, by its collector to said second pin of said first pair of floating pins and by its emitter to said second terminal of said first set of terminals; and said first transistor pair is arranged to provide a conductive path between said first set of terminals and said first pair of floating pins in response to a static charge on said first set of terminals.   
     
     
       17. The ESD device of claim 16 including, said set of floating pins includes a second pair of floating pins;   a second transistor pair;   a second set of terminals having a third terminal and a fourth terminal for connection of said ESD device to provide a discharge path; a first transistor of said second transistor pair is connected by its collector to a first pin of said second pair of floating pins, by its base to a second pin of said second pair of floating pins, and by its emitter to said third terminal and a second transistor of said second transistor pair is connected by its base to said first pin of said second pair of floating pins, by its collector to said second pin of said second pair of floating pins and by its emitter to said fourth terminal; and said second transistor pair is arranged to provide a conductive path between said second set of terminals and said second pair of floating pins in response to a static charge on said second set of terminals.   
     
     
       18. The ESD device of claim 17, including: a third transistor pair;   a first transistor of said third transistor pair is connected by its collector to said first pin of said first pair of floating pins, by its base to said second pin of said first pair of floating pins, and by its emitter to said second terminal of said first set of terminals and a second transistor of said third transistor pair is connected by its base to the said first pin of said first pair of floating pins, by its collector to said second pin of said first pair of floating pins and by its emitter to said second terminal of said first set of terminals; and said third transistor pair is arranged to provide a conductive path between said first set of terminals and said first pair of floating pins in response to a static charge on said first set of terminals.   
     
     
       19. The ESD device of claim 18 including: a fourth transistor pair;   a first transistor of said fourth transistor pair is connected by its collector to said first pin of said second pair of floating pins, by base to said second pin of said second pair of floating pins, and by its emitter to said fourth terminal; and   an second transistor of said fourth transistor pair is connected by base to said first pin of said second pair of floating pins by its collector to said second pin of said second pair of floating pins and by its emitter to said fourth terminal.   
     
     
       20. The ESD device of claim 13 wherein: one transistor of said fourth transistor pair is a NPN transistor and a second transistor of said fourth transistor pair is a PNP transistor.