Three-dimensional integrated circuit stacking

Abstract

A plurality of integrated circuit chips (12) are packaged in a stack of chips in which a number of individual chip layers (10,120,130,132,134) are physically and electrically interconnected to one another and are peripherally sealed to one another to form an hermetically sealed package having a number of input/output pads (137a,139a,141a,156,158,160) on the surface of the upper (132) and lower (134) layers. Each chip layer comprises a chip carrier substrate having a chip cavity (22) on a bottom side and having a plurality of electrically conductive vias (40,42,44) extending completely around the chip cavity. Each substrate is formed with a peripheral sealing strip (46,48) on its top and bottom sides and mounts on its top side a chip that has its connecting pads (14) wire bonded to exposed traces (32,34) of a pattern of traces that are formed on the top side of the substrate and on intermediate layers (16,18,20) of this multi-layer substrate. The traces interconnect with the vias (40,42,44) that extend completely through the substrate, and each via is provided at the top and bottom sides of the substrate with a via connecting pad (40a41b), with the via pads on top and bottom sides all being arranged in identical patterns. Solder on the via pads and on the sealing strips is reflowed to effect a completely sealed package and to interconnect vias in each layer with vias in each other layer.

What is claimed is: 
     
       1. A multi-die package comprising: a plurality of stacked chip layers, each said chip layer comprising:   a carrier substrate having top and bottom sides,   a plurality of electrically conductive vias extending through said carrier substrate between said top and bottom sides, each said via having electrically conductive top and bottom via pads on the top and bottom sides of the carrier substrate, wherein each said via pad is oblong and has a major axis, and wherein the major axis of the pad of the top side of each via is angulated relative to the major axis of the pad of the bottom side of the same via,   a pattern of electrically conductive traces formed on the top side of said carrier substrate, at least some of said traces having an outer end connected to one of said via pads,   a chip mounted on said top side of said substrate and having a plurality of chip pads, and   an electrical connection between each of said chip pads and one of said traces,   said chip layers being arranged in a stack of chip layers with the vias of one carrier substrate aligned with the vias of an adjacent carrier substrate and with the via pads on top and bottom sides of each carrier substrate being electrically connected to via pads on respective bottom and top sides of adjacent carrier substrates.   
     
     
       2. The package of claim 1 wherein each said carrier substrate has a geometric center and wherein each includes at least three elongated alignment openings each having a longitudinal axis that intersects said geometric center, each said opening being positioned near the periphery of said carrier substrate, two of said openings being positioned on opposite sides of said geometric center and having mutually aligned axes and a third one of said openings having an axis that is angulated relative to the axes of said two openings. 
     
     
       3. The package of claim 1 wherein each said carrier substrate includes a continuous peripheral seal strip on both top and bottom sides, the seal strips on the top and bottom sides of each carrier being hermetically sealed to the seal strips on the bottom and top sides, respectively, of adjacent carrier substrates. 
     
     
       4. The package of claim 3 including a lid having a plurality of vias registered with the vias of said carrier substrates and electrically connected thereto, and a continuous peripheral sealing strip on the bottom side of said lid congruent with and sealed to a sealing strip on the top side of an uppermost one of said carrier substrates, thereby providing a fully hermetically sealed package of stacked dies. 
     
     
       5. The package of claim 1 wherein the major axis of the pad of the top side of each via is orthogonal to the major axis of the pad of the bottom side of the same via, and wherein the via pad of the top of one carrier substrate is electrically and mechanically connected to a via pad of the bottom of an adjacent carrier substrate to form a pair of interconnected via pads, and wherein the major axis of the via pad of one pad of said pair is orthogonal to the major axis of the via pad of the other pad of said pair. 
     
     
       6. The package of claim 3 wherein said via pads comprise reflow solder pads, and wherein each carrier substrate includes on its top side a solder flow barrier interposed between the inner end of said leads and said via pads. 
     
     
       7. The package of claim 6 wherein said barrier comprises a thin dielectric cover overlying some of said traces. 
     
     
       8. The package of claim 1 including a lid having a plurality of electrically conductive lid vias aligned with respective ones of the vias in said carrier substrates and extending from bottom to top sides of said lid, each of said lid vias having an electrically conductive lid via pad on top and bottom ends thereof, the bottom pads of the lid vias being electrically connected to top pads of the vias of the uppermost one of said group of carrier substrates. 
     
     
       9. The package of claim 1 wherein at least one of said carrier substrates comprises a plurality of dielectric laminations, at least some of said electrically conductive traces being formed on different ones of said laminations. 
     
     
       10. The package of claim 1 wherein each of a group of said carrier substrates includes a cavity on its bottom side and wherein the chip on the top side of one of said carrier substrates is at least partially received within the cavity on the bottom side of an adjacent carrier substrate. 
     
     
       11. A chip carrier for use in forming a hermetically sealed stacked chip package, said carrier comprising; a carrier substrate having top and bottom sides,   a plurality of electrically conductive vias extending through said substrate between said top and bottom sides, each via of said plurality of vias having a respective electrically conductive top and bottom via pad at said top and bottom sides of said substrate,   a pattern of electrically conductive traces formed on the top side of said substrate, at least some traces of said pattern of electrically conductive traces having an outer end connected to one of said via pads and having an exposed chip-connecting end,   an electrical connection between each of said chip pads and one of said traces,   a respective continuous peripheral seal strip on both said top and bottom sides of said carrier substrate, and   a plurality of elongated alignment non-circular openings in said carrier substrate, each alignment opening of said plurality of alignment openings having a longitudinal axis that intersects the geometric center of said carrier substrate.   
     
     
       12. The chip carrier of claim 11 further including a chip mounted on said top side of said substrate and having a plurality of chip pads. 
     
     
       13. The chip carrier of claim 11 wherein said pattern of electrically conductive traces includes a plurality of electrically conductive traces, each trace of said plurality of electrically conductive traces having an exposed end configured and arranged for connection to a connecting pad of a chip to be mounted on said carrier substrate, and each one of said via pads includes a layer of reflow solder thereon, further including a solder barrier interposed between each of said via pads and the respective one of said exposed chip connecting ends of said plurality of traces. 
     
     
       14. The chip carrier of claim 13 wherein said solder barrier comprises a thin dielectric cover overlying at least some of said plurality of electrically conductive traces. 
     
     
       15. The chip carrier of claim 11 wherein said via pads on said top and bottom sides of said substrate are elongated and have longitudinal axes, and wherein said longitudinal axes of said top and bottom via pads at each via are mutually orthogonal. 
     
     
       16. The chip carrier of claim 11 wherein said carrier substrate includes a chip mounting area on one side, and defines a cavity in and opening to the other side of said substrate. 
     
     
       17. The chip carrier of claim 11 further including a lid member having a plurality of electrically conductive lid vias respectively aligned with vias of said carrier substrate and extending from bottom to top sides of said lid, each one of said plurality of electrically conductive lid vias having an electrically conductive lid via pad at respective top and bottom ends thereof, the bottom via pads of said lid vias being electrically connected to respective top pads of said vias of said carrier substrate. 
     
     
       18. The chip carrier of claim 11 wherein said carrier substrate includes a plurality of dielectric laminations, at least some traces of said pattern of electrically conductive traces being formed on different ones of said plurality of dielectric laminations.