Hierarchical cache system flushing scheme based on monitoring and decoding processor bus cycles for flush/clear sequence control

Abstract

An apparatus for monitoring and decoding processor bus cycles and flushing a second level cache upon decoding a special flush acknowledge cycle. The CPU preferably includes an internal cache and a flush input for receiving a signal commanding the CPU to flush its internal cache. After flushing its cache by performing any necessary cycles to write back dirty data to main memory, the CPU performs a special flush acknowledge cycle to inform external devices that the flush procedure has been completed. A cache controller detects the flush acknowledge cycle and provides a flush signal to the second level cache. The cache controller then provides an end of cycle signal to the CPU to indicate that the flush cycle has been acknowledged.

We claim: 
     
       1. A computer system, comprising: a processor bus for carrying cycles, said processor bus including a plurality of lines for indicating the type of cycle being carried on said processor bus;   a first level write-back cache coupled to said processor bus, wherein said first level cache executes a special flush acknowledge cycle indicating completion of flushing of said first level cache after completion of the flushing of said first level cache, said special flush acknowledge cycle being indicated by driving a particular signal set onto said plurality of cycle type lines of said processor bus; and   a second level cache coupled to said processor bus, said second level cache comprising: cache memory including a clear input for invalidating the data in the cache memory; and   a second level cache controller coupled to said processor bus and said second level cache memory for detecting said flush acknowledge cycle, and for providing a clear signal to said second level cache memory clear input in response to said detection.     
     
     
       2. The computer system of claim 1, wherein said second level cache memory comprises tag RAMs including said clear input for receiving said clear signal. 
     
     
       3. The computer system of claim 1, further comprising: a CPU incorporating said first level cache and including an input for receiving a flush signal, wherein said CPU first flushes its internal cache and then executes said special flush acknowledge cycle after receiving said flush signal.   
     
     
       4. The computer system of claim 3, further comprising: a memory controller, wherein said memory controller includes said second level cache controller and   wherein said processor bus includes further includes a memory I/O signal, a write-read signal, a data-control signal and a plurality of byte enable signals for indicating said special flush acknowledge cycle and   wherein said second level cache controller includes means for monitoring said memory I/O signal, said write-read signal, said data-control signal and said plurality of byte enable signals on said processor bus for detecting said special flush acknowledge cycle, wherein said monitoring means provides a flush acknowledge cycle indication signal when said special flush acknowledge cycle is detected.   
     
     
       5. The computer system of claim 4, wherein said second level cache controller further includes: a processor cycle tracker means coupled to said processor bus for providing signals indicating the start and the end of each cycle; and   means coupled to said processor cycle tracker means, said monitoring means, said processor bus and said CPU for asserting said clear signal to said second level cache memory in response to the beginning of a processor cycle when said flush acknowledge cycle indication signal is asserted, and then for asserting said end of cycle signal to acknowledge said special flush acknowledge cycle.