Current source gate drive circuit for simultaneous firing of thyristors

Abstract

A current source gate drive circuit for simultaneous firing of a set of series or parallel thyristors is described. The circuit includes two current loops, each of which serves as a current transformer primary. Electrically insulating tubes enclose the current loops. Current transformer cores, around which are wound a certain number of secondary turns, surround the current loops, thus magnetically coupling the primary current of the current transformer to the secondary turns. Thyristor gate driver circuits are electrically coupled to the current transformer cores. Each of the thyristor gate driver circuits receives and rectifies ac current signals from the current loops and forms a current pulse train firing signal. Each thyristor gate driver circuit has a corresponding thyristor that is fired by the current pulse train firing signal. The thyristors operate at a high voltage, but are electrically isolated from the current loops by the insulating tubes. A current pulse shaping circuit is connected to the current loops and uses dual resonant LC circuits to generate ac current signals. The current pulse shaping circuit operates in a low voltage region and is electrically isolated from the high voltage region by the insulating tubes. The current pulse shaping circuit is activated by an edge-triggered signal. To prevent misfiring of the thyristors, thyristor firing command logic is used to generate a level-trigger signal. Level-triggered logic is responsive to the level-trigger signal, but not noise or transients, and produces a pulse train enable signal that allows the thyristors to be fired.

We claim: 
     
       1. A current source gate drive circuit for simultaneously firing a set of thyristors, comprising: a first current loop serving as a first current transformer primary and carrying a first current pulse train with a first phase;   a second current loop serving as a second current transformer primary and carrying a second current pulse train with a second phase shifted a half-cycle from said first phase;   a first electrically insulating tube enclosing said first current loop;   a second electrically insulating tube enclosing said second current loop;   a first plurality of current transformer cores surrounding said first current loop;   a second plurality of current transformer cores surrounding said second current loop;   a plurality of thyristor gate drivers, each of said thyristor gate drivers including a first current transformer secondary winding being coupled to one of said first plurality of current transformer cores, and a second current transformer secondary winding being coupled to one of said second plurality of current transformer cores, each of said thyristor gate drivers thereby receiving said first current pulse train and said second current pulse train, each of said thyristor gate drivers rectifying said first current pulse train and said second current pulse train to form a current pulse train firing signal;   a plurality of thyristors, each of said thyristors being coupled to a selected thyristor gate driver of said plurality of thyristor gate drivers and thereby receiving said current pulse train firing signal, said plurality of thyristors operating in a high voltage region and being electrically isolated from said first current loop and said second current loop by said first insulating tube and said second insulating tube; and   a current pulse shaping circuit connected to said first current loop and said second current loop to generate said first current train and said second current pulse train, said current pulse shaping circuit operating in a low voltage region and being electrically isolated from said high voltage region by said first insulating tube and said second insulating tube, said current pulse shaping circuit including   a first current pulse generating circuit coupled to said first current loop and including an LC network for generating said first current pulse train, and   a second current pulse generating circuit coupled to said second current loop and including an LC network for generating said second current pulse train.   
     
     
       2. The current source gate drive circuit of claim 1 wherein said first current pulse generating circuit includes a first capacitor charge circuit and said second current pulse generating circuit includes a second capacitor charge circuit. 
     
     
       3. The current source gate drive circuit of claim 2 wherein said first capacitor charge circuit and said second capacitor charge circuit each include a comparator for comparing a voltage reference signal and a capacitor reference signal to produce a capacitor recharge signal. 
     
     
       4. The current source gate drive circuit of claim 3 wherein said voltage reference signal is modulated to produce a diminished amplitude capacitor re-charge signal that produces a diminished amplitude in said first current pulse train and said second current pulse train. 
     
     
       5. The current source gate drive circuit of claim 4 wherein said first current pulse generating circuit includes a first steep-rise RC circuit for creating a steep rise on the first pulse of said first current pulse train and said second current pulse generating circuit includes a second steep-rise RC circuit for creating a steep rise on the first pulse of said second current pulse train. 
     
     
       6. The current source gate drive circuit of claim 1 further comprising thyristor firing command logic to generate an edge trigger signal for said current pulse shaping circuit and a level-trigger signal for a noise lock-out circuit. 
     
     
       7. The current source gate drive circuit of claim 6 wherein said noise lock-out circuit includes level-triggered logic to generate a pulse train enable signal only in response to said level-trigger signal, said pulse train enable signal enabling said current pulse shaping circuit to apply said first current pulse train to said first current loop and said second current pulse train to said second current loop. 
     
     
       8. The current source gate drive circuit of claim 7 wherein said level triggered logic includes serially connected inverters. 
     
     
       9. The current source gate drive circuit of claim 8 wherein said noise lock-out circuit includes a Schmitt trigger positioned between said thyristor firing command logic and said level-triggered logic. 
     
     
       10. A circuit for firing a plurality of thyristors, comprising: thyristor firing command logic to generate an edge-trigger signal and a level-trigger signal;   edge-triggered logic connected to said thyristor firing command logic, said edge-triggered logic responding to said edge-trigger signal to selectively generate an edge-triggered logic output signal;   noise-lock circuitry connected to said thyristor firing command logic, said noise-lock circuitry including level-triggered logic responsive to said level-trigger signal to selectively generate a pulse train enable signal; and   a current pulse generating circuit, connected to said edge-triggered logic and said noise-lock circuitry, for generating a current pulse signal to fire said plurality of thyristors solely in response to said edge-triggered logic output signal and said pulse train enable signal.   
     
     
       11. The circuit of claim 10 wherein said level-triggered logic includes serially connected inverters. 
     
     
       12. The circuit of claim 10 further comprising a Schmitt trigger positioned between said thyristor firing command logic and said level-triggered logic.