Reproduction error correction circuit for a video reproduction system & the method for operating it

Abstract

A reproduction error correction circuit for a video reproduction system includes a line-storage memory for temporarily storing composite video signal samples, which memory is operated to provide both for time-base correction and for drop-out compensation. The memory is cyclically supplied sequential write addresses descriptive of pixel locations along a horizontal scan line, generated at a rate that tracks any jitter in the input video signal selectively used for writing over the previous contents of the memory. The memory is cyclically supplied sequential read addresses offset 1/2 scan line from the write addresses, generated at a stable rate equal to an average over several scan lines of the rate at which write addresses are generated. This provides for time-base error correction. When a drop-out is detected, overwriting of video signal samples already stored in the single line-storage memory is prohibited. This type of overwrite protection implements automatic replacement of the video signal during periods when drop-out is detected. The phase of the chrominance signal component of the delayed video used for drop-out compensation is adjusted, however, when necessary, to correspond to that required in the replacement signal.

What is claimed is: 
     
       1. A reproduction error correction circuit a video reproduction system comprising: storage means for storing image data of one horizontal scanning period by receiving an image digitized in response to a write clock signal;   write address generating means for sequentially generating write addresses for said storage means in response to said write clock signal;   read address generating means for sequentially generating read addresses for said storage means in response to a read clock signal;   a chrominance signal phase controlling means for controlling the phase of a chrominance signal by receiving a drop-out detecting signal, said read address signal and said write address signal;   a chrominance signal phase inverting means for inverting the phase of the chrominance signal by receiving the output signal of said storage means; and   selecting means for outputting the output signal of said storage means or outputting the output signal of said chrominance signal phase inverting means in response to the output signal of said chrominance signal phase controlling means.   
     
     
       2. A reproduction error correction circuit for a video reproduction system comprising: storage means for storing image data of one horizontal scanning period by receiving an image digitized in response to a write clock signal:   write address generating means for sequentially generating write addresses for said storage means in response to said write clock signal;   read address generating means for sequentially generating read addresses for said storage means in response a read clock signal;   a chrominance signal phase controlling means for controlling the phase of a chrominance signal by receiving a drop-out detecting signal said, read address signal and said write address signal;   a chrominance signal phase inverting means for inverting the phase of the chrominance signal by receiving the output signal of said storage means; and   selecting means for outputting the output signal of said storage means or outputting the output signal of said chrominance signal phase inverting means in response to the output signal of said chrominance signal phase controlling means, wherein said chrominance signal phase controlling means comprises: first write address storage means for temporarily storing the write address corresponding to a starting point of said drop-out detection signal;   second write address storage means for storing the write address signal corresponding to a finishing point said drop-out detection signal;   first comparing means for comparing the read address signal with the write address signal temporarily stored in said first write address storage means and generating a respective output indication of when the read address signal is the same as the write address signal temporarily stored in said first write address storage means;   second comparing means for comparing the read address signal with the write address signal temporarily stored in said second write address storage means and generating a respective output indication of when the read address signal is the same as the write address signal temporarily stored in said secondt write address storage means;   first toggling means for toggling in response to each output indication from said first comparing means;   second toggling means for toggling in response to each output indication from said second comparing means;   gating means for receiving the output signal of said first toggling means and the output signal of said second toggling means and performing an AND operation on the output signal of said first toggling means and the logic complement of the output signal of said second toggling means; and   reset signal generating means for generating a reset signal when said read address matches the write address of a drop-out finishing point, which said reset signal resets said first and second write address storage means to write addresses outside the range of write addresses for said storage means, and which said reset signal clears said first and second toggling means.     
     
     
       3. A reproduction error correction circuit for a video reproduction system as claimed in claim 2, wherein said reset signal generating means comprises: AND operating means for receiving the output signal of said second toggling means and the inverted signal of said gating means mad performing an AND operation thereon;   a first bit latch for temporarily storing the output signal of said AND operating means in response to said read clock signal and outputting the same;   a second bit latch for temporarily storing the inverted output signal of said first bit latch in response to said read clock signal and outputting the same; and   AND operating means for receiving the output signals of said first and second bit latches and an initialization signal and performing an AND operation thereon thus to generate said reset signal.   
     
     
       4. A reproduction error correction circuit for a video reproduction system; which system includes a write clock signal generator for generating a write clock signal that tracks any jitter in an input video signal, a read clock generator for generating a stable read clock signal, and a drop-out detector for generating a drop-out detection signal whenever drop-out occurs in said input video signal; said reproduction error correction circuit for generating a time-base-corrected output video signal, which said output video signal is responsive to said input video signal except whenever a drop-out detection signal occurs and is then provided drop-out compensation; said reproduction error correction circuit comprising; memory for storing image data of one horizontal scanning period, provided with an input port receiving said input video signal as digitized in response to said write clock signal, and provided with an output port;   a write address generator for generating in a prescribed sequence, write addresses for said memory at a rate responsive to said write clock signal;   a read address generator for generating in said prescribed sequence, read addresses for said memory at a rate responsive to said read clock signal, said read addresses corresponding to write addresses generated a portion of a line scanning period earlier;   circuitry for separating the chrominance portion of video signal read from said memory via its output port;   circuitry for selectively changing, between first and second color subcarrier phases, the phase of the chrominance portion of the video signal read from said memory via its output port, thereby to generate a corrected-chrominance-phase signal;   circuitry for combining said corrected-chrominance-phase signal with the luminance portion of the video signal read from said memory via its output port, thereby to generate said time-base-corrected output video signal; and   a chrominance signal phase controlling for controlling the selection of the phase of said corrected-chrominance-phase signal response to said drop-out detecting signal, said read address signal and said write address signal, wherein said chrominance signal phase controller comprises: a first write address latching circuit for temporarily storing the write address corresponding to the start of said drop-out detection signal;   a second write address latching circuit for temporarily storing the write address signal corresponding to the finish of said drop-out detection signal;   a first digital comparator for comparing the read address signal with the write address signal temporarily stored in said first write address latching circuit;   a second digital comparator for comparing the read address signal with the write address signal temporarily stored in said second write address latching circuit;   a first toggling circuit, connected for being toggled in response to the output signal of said first digital comparator indicating that the read address signal is equal to the write address signal temporarily stored in said first write address latching circuit;   a second toggling circuit, connected for being toggled in response to the output signal of said second digital comparator indicating that the read address signal is equal to the write address signal temporarily stored in said second write address latching circuit;   gating circuitry for receiving the output signal of said first toggling circuit and the output signal of said second toggling circuit and performing a first AND operation on the output signal of said first toggling circuit and the logic complement of the output signal of said second toggling circuit; and   reset signal generating circuitry for generating a reset signal when said read address matches the write address of a drop-out finishing point, which reset signal resets said first and second write address latching circuits to write address values outside the address range of said memory for storing image data of one horizontal scanning period, and clears said first and second toggling circuits.     
     
     
       5. A reproduction error correction circuit for a video reproduction system as claimed in claim 4, wherein said gating circuitry comprises: a NOR gate generating a NOR logic response to the output signals of said first and second toggling circuits;   an OR gate generating an OR logic response to said NOR logic response and the output signal of said second toggling circuit; and   a logic inverter complementing said OR logic response to complete said first AND operation.   
     
     
       6. A reproduction error correction circuit for a video reproduction system as claimed in claim 5, wherein said reset signal generating circuitry comprises: a two-input first AND gate, being connected for receiving the output signal of said second toggling means and the OR logic response of said OR gate, and performing a second AND operation thereon;   a first bit latch responding to said read clock signal for temporarily storing the output signal of said two-input first AND gate and outputting the same;   a second bit latch responding to said read clock signal for temporarily storing a logic complement of the output signal of said first bit latch and outputting the same; and   a three-input second AND gate, being connected for receiving an initialization signal and the output signals of said first and second bit latches, and performing a third AND operation thereon thus to generate said reset signal.   
     
     
       7. A reproduction error correction circuit for a video reproduction system as claimed in claim 4, wherein said reset signal generating circuitry comprises: a two-input first AND gate, being connected for receiving the output signal of said second toggling means and the OR logic response of said OR gate, and performing a second AND operation thereon;   a first bit latch responding to said read clock signal for temporarily storing the output signal of said two-input first AND gate and outputting the same;   a second bit latch responding to said read clock signal for temporarily storing a logic complement of the output signal of said first bit latch and outputting the same; and   a three-input second AND gate, being connected for receiving an initialization signal and the output signals of said first and second bit latches, and performing a third AND operation thereon thus to generate said reset signal.   
     
     
       8. A reproduction error correction method for a video reproduction system using a composite video signal comprising luminance and chrominance signal components, said chrominance signal component being formed by the modulation of a color subcarrier which is apt to be suppressed, said method comprising the steps of: temporarily preserving previous video signal portions from scanning lines previous to a current horizontal scanning line, which video signal portions are those most recently received in the absence of drop-out detection signal being generated;   detecting when video signal of a current horizontal scanning line experiences drop-out, for generating a drop-out detection signal;   responsive to said drop-out detection signal replacing video signal, of a current horizontal scanning line with a replacement video signal generated from corresponding video signal, portions of which are preserved from at least one previous horizontal scanning line and are the previous video signal portions most recently received in the absence of drop-out detection signal being generated; and   generating said replacement video signal by substeps comprising: using in said replacement video signal said portions of said previous video signal most recently received in the absence of drop-out detection signal being generated, except for chrominance signal components of said previous video signal taken from an odd number of scan lines back;   inverting the phase of the chrominance signal component of said previous video signal taken from an odd number of scan lines back that accompanied luminance signal component used in said replacement video signal; and   using the resulting inverted-phase chrominance signal component in said replacement video signal.     
     
     
       9. A reproduction error correction method for a video reproduction system using a line-storage memory for storing composite video signal comprising luminance and chrominance signal components, said chrominance signal component being formed by the modulation of a color subcarrier which is apt to be suppressed, said method comprising the steps of: detecting when video signal of a current horizontal scanning line experiences drop-out, for generating a drop-out detection signal;   digitizing the composite video signal at a rate phase-locked to a multiple of frequency of synchronizing information contained within the composite video signal;   generating a sequence of write addresses for the line-storage memory, which write addresses are generated at the same rate as the composite video signal is digitized;   writing the digitized composite video signal into said line-storage memory only when said drop-out detection signal is not generated;   generating a sequence of read addresses for the line-storage memory, which read addresses are generated at a fixed rate the average of which taken over several scan lines is the same as the average of the rate at which write addresses are generated; and   generating an output video signal from the composite video signal read from the line-storage memory by substeps comprising: counting the number of scan line durations modulo-two that said drop-out detection signal is generated;   responsive to the modulo-two count of the number of scan line durations that said drop-out detection signal is generated being zero, generating said output video signal so it has respective luminance and chrominance signal components similar to the composite video signal read from the line-storage memory; and   responsive to the modulo-two count of the number of scan line durations that said drop-out detection signal is generated being one, generating said output video signal so it has a luminance signal component similar to the composite video signal read from the line-storage memory and has a chrominance signal component of amplitude similar to that of the chrominance signal component of the composite video signal read from the line-storage memory, but of opposite phasing respective to color burst.     
     
     
       10. A reproduction error correction method for a video reproduction system wherein a video signal of a current horizontal scanning line is replaced with video signal from a horizontal scanning line one previous to the current horizontal scanning line, inverting the phase of the chrominance subcarrier of said horizontal scanning line one previous to the current horizontal scanning line, when a drop-out is generated within one horizontal scanning period; and wherein, when a drop-out is generated within an interval extending more than one horizontal scanning period to another, in the interval from the generation point of the drop-out until the point one horizontal scanning period letter in time, the video signal of a current horizontal scanning line is replaced with the video signal from the horizontal scanning line one previous to the current horizontal scanning line, inverting the phase of the chrominance subcarrier of said horizontal scanning line one previous to the current horizontal scanning line, and, in the interval after the point of one horizontal scanning period later in time than the generation point of the drop-out, the video signal of the next current horizontal scanning line is replaced with the video signal from the horizontal scan line two horizontal scanning lines previous thereto, maintaining the phase of the chrominance subcarrier of the video signal from the horizontal scan line two horizontal scanning lines previous.