First-in-first-out buffer memory

Abstract

Disclosed is the FIFO buffer memory, comprising a core memory 12 having a dual port structure, for substantially storing data, first and second address decoders 13 and 14 responsive to read and write clock signals, for producing addresses indicative of directing locations in the core memory when data is written in the core memory or when the data is read from the core memory, and a status detector 15 for generating memory status signals indicating whether the data can be written in the FIFO buffer memory or whether the data can be read from the FIFO buffer memory, i.e. full and empty flags. The buffer memory can be embodied without use of complicated circuits such as address counter, address register and comparator, which can be operated at high speed and embodied with high-density integration.

What is claimed is: 
     
       1. A first-in first-out buffer memory comprising: a core memory having a dual port, for substantially storing data;   first and second address decoders responsive to read and write clock signals, for producing addresses indicative of directing a location in the core memory, when data is written in the core memory, or when the data is read from the core memory; and   a status detector for generating memory status signals indicating whether the data can be written in the core memory or whether the data can be read from the core memory,   said status detector comprising,   first and second flip-flops for providing input signals thereof to output terminals thereof in accordance with the write and read clock signals, respectively, each having a clear terminal and a clock terminal;   a multiplexer for receiving the output signals of the flip-flops and selecting one of them in response to a selection control signal;   a phase detector for generating the selection control signal in response to the write and read clock signals to control selecting operation of the multiplexer;   a first AND gate for receiving output data of the multiplexer and generating a full flag on the basis of AND logic function thereof;   a NOR gate for receiving the output data of the multiplexer and generating an empty flag on the basis of NOR logic function thereof;   an increment circuit for incrementing the output data of the multiplexer by one and providing incremented signal to the input of the first flip-flop; and   a decrement circuit for decrementing the output data of the multiplexer by one and providing decremented signal to the input of the second flip-flop.   
     
     
       2. The first-in first-out buffer memory as defined in claim 1, wherein each of said address decoders comprises a plurality of flip-flops, each flip-flop having one input, one output and one clock terminal, and wherein each of the flip-flops is preset or cleared in response to an externally applied clear signal and provides an input signal thereof to the output thereof in accordance with the write and read clock signal. 
     
     
       3. The first-in first-out buffer memory as defined in claim 1, wherein said phase detector comprises a third flip-flop having an input terminal connected to a source voltage supply, for generating a high or low level signal in synchronizing with the write clock signal, a fourth flop-flop having an input terminal connected to a ground, for generating a high or low signal in synchronizing with the read clock signal, a second AND gate for receiving output of the third flip-flop and the clear signal and providing a preset control signal generated on the basis of AND logic function thereof to a preset terminal of the fourth flip-flop, and a third AND gate for receiving output of the fourth flip-flop and the clear signal and providing a clear control signal generated on the basis of AND logic function thereof to a clear terminal of the first flip-flop.