Data processing with improved register bit structure

Abstract

A data processing system (10) includes a register bit structure (27) which can be hard-wired (37, 39) but is also selectively configureable for read/write operation.

What is claimed is: 
     
       1. A data processing system, comprising: data processing circuitry for performing data processing operations on data provided thereto;   a peripheral device connected to said data processing circuitry for communication with said data processing circuitry;   said data processing circuitry including a register for holding data therein, said register including a register bit structure having a data input and a data output, said register bit structure also including a latch having an input connected to said data input and having an output, said register bit structure including a terminal connected to said latch output, and said register bit structure also including a multiplexer having an output connected to said data output, said multiplexer having a plurality of inputs, one of said multiplexer inputs connected to said latch output, and another of said multiplexer inputs connected to said terminal; and   wherein said multiplexer has a control input and connects said data output to said terminal when said control input indicates that said data processing circuitry is operating in a functional mode, and wherein said multiplexer connects said data output to said latch output when said control input indicates that said data processing circuitry is operating in an emulation mode or a test mode.   
     
     
       2. A data processing system, comprising: data processing circuitry for performing data processing operations on data provided thereto;   a peripheral device connected to said data processing circuitry for communication with said data processing circuitry;   said data processing circuitry including a register for holding data therein, said register including a register bit structure having a data input and a data output, said register bit structure including a latch having an input connected to said data input and having an output, said register bit structure including a terminal connected to a fixed logic level, and said register bit structure including a multiplexer having an output and a plurality of inputs, said multiplexer output connected to said data output, one of said multiplexer inputs connected to said latch output, and another of said multiplexer inputs connected to said terminal; and   wherein said multiplexer has a control input and connects said data output to said terminal when said control input indicates that said data processing circuitry is operating in a functional mode, and wherein said multiplexer connects said data output to said latch output when said control input indicates that said data processing circuitry is operating in an emulation mode or a test mode.   
     
     
       3. The system of claim 2, wherein said latch is a shift register latch having a further input for connection into a serial scan path. 
     
     
       4. The system of claim 3, wherein said further input of said shift register latch is coupled to said output of said shift register latch to permit data from said further input to be selectively latched at said output of said shift register latch. 
     
     
       5. A data processing system, comprising: data processing circuitry for performing data processing operations on data provided thereto;   a peripheral device connected to said data processing circuitry for communication with said data processing circuitry;   said data processing circuitry including a register for holding data therein, said register including a register bit structure having a data input and a data output, said register bit structure including a latch having an input connected to said data input and having an output, said register bit structure including a terminal and a circuit for selectively gating said latch output to said terminal, and said register bit structure including a multiplexer having an output and a plurality of inputs, said multiplexer output connected to said data output, said latch output connected to one of said multiplexer inputs, and said terminal connected to another of said multiplexer inputs; and   wherein said multiplexer has a control input and connects said data output to said terminal when said control input indicates that said data processing circuitry is operating in a functional mode, and wherein said multiplexer connects said data output to said latch output when said control input indicates that said data processing circuitry is operating in an emulation mode or a test mode.   
     
     
       6. An electronic device, comprising: data processing circuitry for performing data processing operations on data provided thereto;   information storage circuitry for storing therein information used by said data processing circuitry, said information storage circuitry including a plurality of registers, one of said registers including a register bit structure having a data input and a data output, said register bit structure including a latch having an input connected to said data input and having an output, said register bit structure including a terminal connected to said latch output, and said register bit structure including a multiplexer having an output connected to said data output, said multiplexer having a plurality of inputs, one of said multiplexer inputs connected to said latch output, and another of said multiplexer inputs connected to said terminal; and   wherein said multiplexer has a control input and connects and data output to said terminal when said control input indicates that said data processing circuitry is operating in a functional mode, and wherein said multiplexer connects said data output to said latch output when said control input indicates that said data processing circuitry is operating in an emulation mode or a test mode.   
     
     
       7. The device of claim 6, wherein said latch is a shift register latch having a further input for connection into a serial scan path. 
     
     
       8. The device of claim 7, wherein said further input of said shift register latch is coupled to said output of said shift register latch to permit data from said further input to be selectively latched at said output of said shift register latch. 
     
     
       9. An electronic device, comprising: data processing circuitry for performing data processing operations on data provided thereto;   information storage circuitry for storing therein information used by said data processing circuitry, said information storage circuitry including a plurality of registers, one of said registers including a register bit structure having a data input and a data output, said register bit structure including a latch having an input connected to said data input and having an output, said register bit structure including a terminal connected to a fixed logic level, and said register bit structure including a multiplexer having an output and a plurality of inputs, said multiplexer output connected to said data output, one of said multiplexer inputs connected to said latch output, and another of said multiplexer inputs connected to said terminal; and   wherein said multiplexer has a control input and connects said data output to said terminal when said control input indicates that said data processing circuitry is operating in a functional mode, and wherein said multiplexer connects said data output to said latch output when said control input indicates that said data processing circuitry is operating in an emulation mode or a test mode.   
     
     
       10. An electronic device, comprising: data processing circuitry for performing data processing operations on data provided thereto;   information storage circuitry for storing therein information used by said data processing circuitry, said information storage circuitry including a plurality of registers, one of said registers including a register bit structure having a data input and a data output, said register bit structure including a latch having an input connected to said data input and having an output, said register bit structure including a terminal and a circuit for selectively gating said latch output to said terminal, and said register bit structure including a multiplexer having an output and a plurality of inputs, said multiplexer output connected to said data output, one of said multiplexer inputs connected to said latch output, and another of said multiplexer inputs connected to said terminal; and   wherein said multiplexer has a control input and connects said data output to said terminal when said control input indicates that said data processing circuitry is operating in a functional mode, and wherein said multiplexer connects said data output to said latch output when said control input indicates that said data processing circuitry is operating in an emulation mode or a test mode.