Delay circuit for digital signal processing

Abstract

A delay circuit comprises cascade-connected first through third inverters. The second inverter comprises a first resistor one terminal of which is connected to an output of the first inverter; a P-channel MOS transistor a gate of which is connected to the other terminal of the first resistor, and a source of which receives a power supply voltage; an N-channel MOS transistor a gate of which is connected to the other terminal of the first resistor, a source of which receives a ground voltage, and a drain of which is connected to a drain of the P-channel MOS transistor; and a capacitor one terminal of which is connected to the other terminal of the first resistor, and the other terminal of which is connected to the other terminal of a current path of the P-channel MOS transistor. The P-channel MOS transistor and the N-channel MOS transistor switch among a first state in which the P-channel MOS transistor operates in a saturation region and the N-channel MOS transistor operates in a cutoff region, a second state in which the P-channel MOS transistor operates in an active region and the N-channel MOS transistor operates in the active region, and a third state in which the P-channel MOS transistor operates in the cutoff region and the N-channel MOS transistor operates in the saturation region.

What is claimed is: 
     
       1. A delay circuit comprising: a first inverter for inverting a signal level of an input signal;   a second inverter comprising:   a first resistor, one terminal of which is connected to an output terminal of the first inverter;   a P-channel MOS transistor, a gate of which is connected to the other terminal of the first resistor and one terminal of a current path which receives a first voltage;   an N-channel MOS transistor, a gate of which is connected to the other terminal of the first resistor, one terminal of a current path which receives a second voltage, and the other terminal of the current path which is connected to the other terminal of the current path of the P-channel MOS transistor; and   a capacitor, one terminal of which is connected to the other terminal of the first resistor for forming a capacitor-resistor (CR) circuit determining a delay by charging and discharging thereof, and the other terminal of which is connected to the other terminal of the current path of the P-channel MOS transistor; and   a third inverter, an input terminal of which is connected to a connection node between the current path of the P-channel MOS transistor and the current path of the N-channel MOS transistor, and for inverting a signal level of an output signal of the second inverter, whereby at least one of the P-channel MOS transistor and the N-channel MOS transistor operates in a cutoff region depending on a voltage of an output signal of the first inverter,   wherein a threshold value VTP2 of the P-channel MOS transistor of said second inverter and a threshold value VTN2 of the N-channel MOS transistor of said second inverter satisfy the following equations:   -2Vdd/5<VTP2<-Vdd/5       Vdd/5<VTN2<2Vdd/5       wherein Vdd represents a difference between the first and second voltages,   each of the first and third inverters comprises a P-channel MOS transistor and an N-channel MOS transistor whose current paths are cascade-connected,   wherein a threshold value VTP1 of the P-channel MOS transistor and a threshold value VTN1 of the N-channel MOS transistor of the first inverter and a threshold value VTP3 of the P-channel MOS transistor and a threshold value VTN3 of the N-channel MOS transistor of the third inverter satisfy the following equations:   -Vdd/5<VTP1<-Vdd/6                                         (1)       Vdd/6<VTN1<Vdd/5                                           (2)       -Vdd/5<VTP3<-Vdd/6                                         (3)       Vdd/6<VTN3<Vdd/5                                           (4).       
     
     
       2. A delay circuit, comprising: delay means, said delay means comprising: a first resistor;   a P-channel MOS transistor including a gate connected to one terminal of the first resistor and one terminal of a current path which receives a first voltage;   an N-channel MOS transistor including a gate connected to the one terminal of the first resistor, one terminal of a current path which receives a second voltage and the other terminal of the current path which is connected to the other terminal of the current path of the P-channel MOS transistor; and   a capacitor, one terminal of which is connected to the other terminal of the first resistor for forming a capacitor-resistor (CR) circuit determining a delay by charging and discharging thereof, and the other terminal of which is connected to the other terminal of the current paths of the P-Channel MOS transistor;     inverting/waveform shaping means coupled to the delay means for inverting a signal level of an output signal of the delay means and shaping a waveform of the output signal; and   means for receiving an input digital signal, inverting a signal level of the digital signal, supplying the inverted signal to the other terminal of the resistor to set the P-channel MOS transistor and the N-channel MOS transistor to a predetermined state, said predetermined state including one of:     a first state wherein the P-channel MOS transistor operates in a saturation region and the N-channel MOS transistor operates in a cutoff region;   a second state wherein the P-channel MOS transistor operates in an active region and the N-channel MOS transistor operates in the active region; and   a third state wherein the P-channel MOS transistor operates in the cutoff region and the N-channel MOS transistor operates in the saturation region, to thereby generate at an output terminal of the inverting/waveform shaping means a signal obtained by delaying the input digital signal for a predetermined period of time,   wherein a threshold value VTP2 of the P-channel MOS transistor of said delay means and a threshold value VTN2 of the N-channel MOS transistor of said delay means satisfy the following equations:   -2Vdd/5<VTP2<-Vdd/5       Vdd/5<VTN2<2Vdd/5       wherein Vdd represents a difference between the first and second voltages,   each of the means for receiving and the inverting/waveform shaping means comprises a P-channel MOS transistor and an N-channel MOS transistor whose current paths are cascade-connected,   wherein a threshold value VTP1 of the P-channel MOS transistor and a threshold value VTN1 of the N-channel MOS transistor of the means for receiving and a threshold value VTP3 of the P-channel MOS transistor and a threshold value VTN3 of the N-channel MOS transistor of the inverting/waveform shaping means satisfy the following equations:   -Vdd/5<VTP1<-Vdd/6                                         (1)       Vdd/6<VTN1<Vdd/5                                           (2)       -Vdd/5<VTP3<-Vdd/6                                         (3)       Vdd/6<VTN3<Vdd/5                                           (4).