High performance channel adapter having a pass through function

Abstract

An adapter for attachment to the bus or video display of a personal computer, workstation or like devices to a high performance parallel interface (HIPPI)channel of a host computer. In a system having at least three devices to be connected to a high performance parallel interface in a "Daisy chain," each of the devices has an adapter capable of both sending and receiving bursts of data with a data click. Each adapter includes an inbound receiver connected to the channel for receiving bursts of data and data clock and a decoder for decoding routing information contained in the bursts of data. A pass through logic circuit is connected to the decoder for interpreting the routing information. A first latch is connected to the inbound receiver for temporarily storing data bursts. A second latch is connected to the first latch for accepting data bursts when the routing information identifies a device to which the adapter is connected. A data selector is connected to the first latch for selecting data from the device or from the first latch. An outbound transmitter is connected to the channel for transmitting bursts of data and a data clock, the outbound transmitter also being connected to the data selector for transmitting data bursts to the next adapter in the Daisy chain from the first latch when the routing information does not identify the device.

Having thus described our invention, what we claim as new and desire to secure by Letters Patent is as follows: 
     
       1. An adapter for connecting at least three devices to a high performance parallel interface channel connected in a "Daisy chain", each of said devices being capable of both sending and receiving bursts of data with a data clock, said adapter comprising: inbound receiver means connected to said channel for receiving said bursts of data and data clock;   decoder means for decoding routing information contained in said bursts of data;   pass through logic means connected to said decoder means for interpreting said routing information;   first latch means connected to said inbound receiver means for temporarily storing data bursts;   second latch means connected to said first latch means for accepting data bursts when said routing information identifies a device to which the adapter is connected;   data selector means connected to said first latch means for selecting data from said device or from said first latch means;   outbound transmitter means connected to said channel for transmitting bursts of data and a data clock, said outbound transmitter means also being connected to said data selector means for transmitting data bursts from said first latch means when said routing information does not identify said device.   
     
     
       2. The adapter recited in claim 1 further comprising clock synchronizing means connected to receive said data clock from said inbound receiver means and passing said data clock directly to said outbound transmitter means when said routing information does not identify said device.