Structure and fabrication method for a thin film transistor

Abstract

A structure and fabrication method for a thin film transistor which is suitable for an SRAM memory cell. The thin film transistor structure includes an insulating substrate and a semiconductor layer formed as a wall on the insulation substrate. A gate insulation film is formed on the semiconductor layer and over the entire surface of the insulation substrate. A gate electrode formed on the gate insulation film at the center part of the semiconductor layer. Impurity regions are formed in the semiconductor layer on both sides of the gate electrode.

What is claimed is: 
     
       1. A method for fabricating a thin film transistor comprising the steps of: forming a semiconductor layer having a shape of a wall on an insulating substrate, including the steps of: depositing an insulation film having a thickness equal to a desired height of the wall on the insulating substrate;   removing portions of the insulation film so as to leave the insulation film on one side of the substrate and centered on a part which will be an active region of a transistor;   forming a semiconductor layer in the shape of a wall at the side wall of the insulation film by anisotropic etching of the semiconductor layer; and   removing the insulation film;   forming a gate insulation film on the surface of the insulating substrate and the semiconductor layer formed thereon;   forming a gate electrode on the gate insulation film over a center part of the semiconductor layer; and,   forming impurity regions in the semiconductor layer on both sides of the gate electrode.     
     
     
       2. The method as claimed in claim 1, wherein the insulation film is formed of a nitride film, and is removed with H 3  PO 4 . 
     
     
       3. The method as claimed in claim 1, wherein the semiconductor layer includes a polysilicon layer. 
     
     
       4. The method as claimed in claim 1, wherein the gate insulation film includes a silicon oxide film. 
     
     
       5. The method as claimed in claim 1, wherein the step of forming the gate electrode further comprises the steps of: depositing a conductive layer on the gate insulation film; and   selectively removing the conductive layer to form the gate electrode.   
     
     
       6. The method as claimed in claim 5, wherein the gate electrode is positioned on the center of the semiconductor layer in a perpendicular relationship to a longitudinal direction thereof. 
     
     
       7. The method as claimed in claim 1 wherein the conductive layer includes a doped polysilicon layer. 
     
     
       8. The method as claimed in claim 1, wherein the step of forming the impurity regions further comprises the step of injecting impurity ions into the semiconductor layer on both opposite sides of the gate electrode using the electrode as a mask.