Method and apparatus for implementing a PCMCIA auxiliary port connector for selectively communicating with peripheral devices

Abstract

Circuitry and methods are provided for a standardized serial interface. The interface uses auxiliary port connector pin of a device conforming to the Personal Computer Memory Card International Association (PCMCIA) standard as a serial bus. Protocols are provided that allow a host computer to selectively connect to and communicate with either the PCMCIA based device or with devices connected to the serial bus. The circuitry and protocols support a daisy-chain of multiple devices from a single PCMCIA based device.

We claim: 
     
       1. Circuitry for a host computer to selectively communicate with at least two peripheral devices via an expansion slot, the circuitry comprising: a first peripheral device adapted for coupling to the expansion slot, the first peripheral device including: circuitry for performing a first peripheral task; interface circuitry coupling the first peripheral device to the host computer for transferring data therebetween;   an auxiliary port having a DATA --  FROM --  HOST line, a DATA --  TO --  HOST line, and a CONTROL line;   a data path coupling the interface circuitry to the DATA --  FROM --  HOST line, so that data transmitted by the host computer through the interface circuitry is serially transmitted on the DATA --  FROM --  HOST line; and   switching circuitry coupled to the interface circuitry, to the circuitry for performing a first peripheral task, and to the DATA --  TO --  HOST and CONTROL lines, the switching circuitry responsive to a control signal asserted on the CONTROL line, and selectively changeable between a first state wherein the circuitry for performing a first peripheral task is connected to the interface circuitry and the DATA --  TO --  HOST line is disconnected from the interface circuitry, and a second state wherein the circuitry for performing a first peripheral task is disconnected from the interface circuitry and the DATA --  TO --  HOST line is connected to the interface circuitry; and     a second peripheral device coupled to the auxiliary port of the first peripheral device, the second peripheral device including: circuitry for performing a second peripheral task; and   control circuitry coupled to the circuitry for performing a second peripheral task and to the DATA --  TO --  HOST, DATA --  FROM --  HOST, and CONTROL lines, so that the control circuitry asserts a control signal on the CONTROL line responsive to a first predetermined data sequence on the DATA --  FROM --  HOST line, and removes the control signal from the CONTROL line responsive to a second data sequence on the DATA --  FROM --  HOST line.     
     
     
       2. The circuitry of claim 1 wherein the interface circuitry comprises circuitry operable in accordance with PCMCIA expansion slot specifications. 
     
     
       3. The circuitry of claim 2 wherein the PCMCIA expansion slot is a Type I PCMCIA slot, a Type II PCMCIA slot, or a Type III PCMCIA slot. 
     
     
       4. The circuitry of claim 1 wherein the first peripheral device is a FAX/modem. 
     
     
       5. The circuitry of claim 1 wherein the second peripheral device comprises circuitry for receiving data transmitted via electromagnetic signals. 
     
     
       6. The circuitry of claim 5 wherein the second peripheral device is selected from the group consisting of a pager, an electronic mail receiver, a network interface card and a GPS receiver. 
     
     
       7. The circuitry of claim 1 wherein the second peripheral device comprises circuitry for transmitting data via electromagnetic signals. 
     
     
       8. The circuitry of claim 7 wherein the second peripheral device is a network interface card. 
     
     
       9. The circuitry of claim 1 wherein each of the first and second predetermined data sequences comprise an attention code followed by a command code. 
     
     
       10. The circuitry of claim 1 wherein the control circuitry is a microcontroller, a microprocessor, a microsequencer, or a programmable logic device. 
     
     
       11. The circuitry of claim 1 wherein the interface circuitry and the switching circuitry are integrated into one or more chips of a chip set. 
     
     
       12. The circuitry of claim 1 wherein the data path coupling the interface circuitry to the DATA --  FROM --  HOST line further comprises parallel-to-serial data conversion circuitry. 
     
     
       13. The circuitry of claim 1 wherein the switching circuitry comprises a multiplexer circuit. 
     
     
       14. Circuitry for selectively establishing a data path between a host computer and either a first device mounted on a peripheral card coupled to an expansion slot of a host computer, or a second device coupled to an auxiliary port of the peripheral card, the circuitry comprising: interface circuitry coupling the peripheral card to the host computer for transferring data therebetween;   a DATA --  FROM --  HOST line coupled to the auxiliary port;   a data path coupled between the interface circuitry, and the DATA --  FROM --  HOST line, the data path operative to serially transmit on the DATA --  FROM --  HOST line data transmitted by the host computer to the peripheral card;   a DATA --  TO --  HOST line coupled to the auxiliary port;   a CONTROL line coupled to the auxiliary port;   circuitry for biasing the CONTROL line to a predetermined, non-asserted state when the second device is not coupled to the auxiliary port; and   switching circuitry coupled to the interface circuitry, to the first device, and to the DATA --  TO --  HOST and CONTROL lines, the switching circuitry responsive to a control signal on the CONTROL line and selectively changeable between a first state wherein the first device is connected to the interface circuitry and the DATA --  TO --  HOST line is disconnected from the interface circuitry, and a second state wherein the first device is disconnected from the interface circuitry and the DATA --  TO --  HOST line is connected to the interface circuitry to thereby connect the second device to the host computer.   
     
     
       15. Circuitry for controlling switching circuitry of a peripheral card coupled to an expansion slot of a host computer, the switching circuitry selectably connecting a data path between a host computer and either a first device mounted on the peripheral card, or a second device coupled to an auxiliary port of the peripheral card, the circuitry comprising: circuitry for receiving serial data from the host computer via the auxiliary port of the peripheral card;   circuitry for comparing received serial data with a plurality of preselected command codes; and   circuitry for sending a control signal to the switching circuitry via the auxiliary port of the peripheral card, so that the control signal is asserted when the received serial data matches a first preselected one of the command codes, and so that the control signal is released when the received serial data matches a second preselected one of the command codes.   
     
     
       16. The circuitry of claim 15 wherein the circuitry for receiving serial data, the circuitry for comparing the serial data to preselected command codes, and the circuitry for asserting the control signal is a microcontroller, a microprocessor, a microsequencer, or a programmable logic device. 
     
     
       17. The circuitry of claim 15 wherein in response to a preselected one of the command codes, data is serially transmitted from the second device to the host computer via the auxiliary port and switching circuitry of the peripheral card. 
     
     
       18. A method for a host computer to selectively communicate with a first peripheral device coupled to the host computer via an expansion slot, and a second peripheral device coupled to an auxiliary port of the first peripheral device, the first and second peripheral devices including circuitries for performing first and second peripheral tasks respectively, the method comprising the steps of: transmitting data from the host computer to the second peripheral device at substantially the same time as the data is transmitted to the first peripheral device;   transmitting a preselected data sequence representing a command code from the host computer to the first and second peripheral devices;   generating a control signal by the second peripheral device responsive to the second peripheral device receiving a first preselected data sequence from the host;   changing states of switching circuitry within the first peripheral device responsive to the control signal, wherein the states of the switching circuitry include a first state wherein the circuitry performing the first peripheral task is coupled to the host computer and the circuitry performing a second peripheral task is disconnected from the host computer, and a second state wherein the circuitry performing the first peripheral task is disconnected from the host computer and the circuitry performing a second peripheral task is connected to the host computer.   
     
     
       19. The method of claim 18 further including the step of transmitting an acknowledgement from the circuitry for performing a second peripheral task to the host computer after the step of generating the control signal and the step of changing the state of the switching circuitry. 
     
     
       20. The method of claim 18 further including the step of releasing the control signal by the second peripheral device in response to the second peripheral device receiving a second preselected data sequence from the host computer. 
     
     
       21. The method of claim 18 wherein the step of providing data to the second peripheral device includes a step of converting the data to a serial bit stream. 
     
     
       22. The method of claim 18 wherein the step of sending a preselected data sequence comprises sending an ASCII "break" code followed by a preselected data value. 
     
     
       23. The method of claim 18 further including a step of biasing the control signal to a predetermined, default state in the event the second peripheral device is uncoupled from the auxiliary port of the first peripheral device.