One dimensional silicon quantum wire devices and the method of manufacture thereof

Abstract

A silicon quantum wire transistor. A silicon substrate is sub-etched leaving a thin ridge (≦500 Å tall by ≦500 Å wide) of silicon a quantum wire, on the substrate surface. An FET may be formed from the quantum wire by depositing or growing gate oxide and depositing gate poly. After defining a gate, the source and drain are defined. Alternatively, an optically activated transistor is formed by defining an emitter and collector and providing a path for illumination to the wire.

We claim: 
     
       1. A method of forming a transistor in a silicon substrate, said method comprising the steps of: a) forming a plurality of device regions in a surface of said silicon substrate;   b) sub-etching away said surface of said silicon substrate to form a sub-etched surface in said plurality of device regions, sub-etching the surface comprising the steps of:   1) depositing a plurality of oxide pads on said surface,   2) forming a polysilicon layer on said plurality of oxide pads along the sides of said pads and on said substrate,   3) Reactive Ion Etching said polysilicon layer from said pads and said surface, whereby sidewalls of polysilicon remain along the sides of at least one of said plurality oxide pads,   4) removing said plurality of oxide pads, and,   5) Reactive ion etching to remove said sidewalls and said silicon surface simultaneously, such that a plurality of ridges remain above the sub-etched surface beneath each said sidewall, each of said plurality of ridges being ≦500 Å tall and ≦500 Å wide and being a quantum wire; and,   c) forming at least 2 conductive regions in each said quantum wire, said at least 2 conductive regions being conduction regions of said transistor, whereby when said transistor is conducting current and the length of said quantum wire between said conduction regions is the primary current path for said current through said transistor.     
     
     
       2. The method of claim 1 further comprising: d) forming a FET gate on at least one said quantum wire, said FET gate formed by the steps of:   1) forming a gate oxide layer over said quantum wire and said surface; and   2) forming said FET gate on said gate oxide over said at least one quantum wire.   
     
     
       3. The method of claim 1 wherein the step (c) of forming at least 2 conductive regions forms a transistor, and comprises the steps of: 1) forming a gate oxide layer over each said quantum wire and said surface; and   2) forming a gate on said gate oxide over each said quantum wire, said gate being formed between said at least 2 conductive regions.     
     
     
       4. A method of forming a transistor in a silicon substrate, said method comprising the steps of: a) forming a device region in a surface of said silicon substrate;   b) forming at least one polysilicon line on said device region;   c) simultaneously sub-etching said at least one polysilicon line and the surface of the substrate in said device region until said at least one polysilicon line is etched away to form a sub-etched surface, each said at least one polysilicon line masking said surface such that a ridge is formed therebeneath, said ridge extending above the sub-etched surface, each said ridge forming a quantum wire; and,   d) forming a conduction region at each end of each said quantum wire.   
     
     
       5. The method of claim 4 wherein each said ridge is ≦500 Å tall and ≦500 Å wide. 
     
     
       6. The method of claim 4 wherein the step (b) of forming at least one polysilicon line comprises the steps of: 1) forming an oxide pad on said surface;   2) depositing a polysilicon layer on said surface, said polysilicon layer covering said oxide pad;   3) etching said polysilicon layer such that polysilicon sidewalls remain alongside said oxide pad; and   4) removing said oxide pad.   
     
     
       7. The method of claim 6 wherein a source is a conduction region at one wire end and a drain is a conduction region at an opposite wire end. 
     
     
       8. The method of claim 7 wherein the step (d) of forming said source and said drain includes implanting a dopant in said quantum wire such that an FET formed in said quantum wire is a depletion mode FET. 
     
     
       9. The method of claim 7 further including before the conduction region forming step (d) the step of: c1) forming a gate over at least one said quantum wire.   
     
     
       10. The method of claim 9 wherein the step (c1) of forming the gate comprises the steps of: 1) forming a gate oxide layer over each said quantum wire;   2) depositing a polysilicon gate layer on said gate oxide layer; and,   3) selectively removing said polysilicon gate layer to define said gate.   
     
     
       11. The method of claim 10 wherein the device region is defined by forming field oxide. 
     
     
       12. The method of claim 11 wherein at least one gate is formed over at least two quantum wires and a parasitic FET is formed between said at least two quantum wires. 
     
     
       13. The method of claim 6 wherein a collector is formed by a conduction region at one quantum wire end and an emitter is formed by a conduction region at an opposite end.