PLL timing generator with voltage controlled oscillator

Abstract

A phase lock loop timing generator including a voltage controlled oscillator as a current-limited ring oscillator composed of multistage inverters connected in series in a ring form using a phase lock loop. From nodes of the inverters, φ0 to φ8 signals are obtained and an AND or OR of the signals are calculated to generate an internal timing. The obtained timing pulse is defined by % of a clock cycle of a reference clock signal and thus a timing depending on an external cycle can be set. Further, a timing prior to the clock edge of the reference clock signal can be generated and by using this timing, an effective current cut of an input buffer can be performed. Hence, timing generation proportional to the external clock cycle without being affected by a production process or the like provides a flexible timing design.

What is claimed is: 
     
       1. A phase lock loop timing generator, comprising: a phase comparator, a charging pump, a low-pass filter, and a voltage controlled oscillator (VCO), the phase comparator, the charging pump and the low-pass filter connected in a series arrangement and configured to detect a phase difference between an external clock signal and an internal clock signal and based on the detected phase difference, and to generate an input voltage Vin for the VCO,   the VCO including a voltage-current converter and a current-limited ring oscillator, in the voltage-current converter, a variation of the input voltage Vin being converted into control currents Ip and In, the current-limited ring oscillator having a plurality of inverters connected in series in a ring arrangement,   wherein phase-shifted signals output from nodes of the inverters are logically calculated to produce clock cycle proportional pulses (CCPP) proportional to a clock cycle of the external clock signal cycle,   buffers, connected on a one-to-one basis to the nodes of the inverters, for making loads of the inverters uniform to equalize delay times, and   a delay circuit connected to the buffers for providing a clock edge lookahead pulse (CELP) which is equal to a minimum pulse width of the internal clock signal,   wherein by using the phase-shifted signals output from the nodes of first and second predetermined stages of the inverters from which the internal clock signal is output, a timing prior to a reference clock edge is generated.   
     
     
       2. A phase lock loop timing generator, as recited in claim 1, wherein the number of the inverters is equal to nine, and wherein a plurality of signals, φ0 to φ8 at internal nodes of the inverters in the current-limited ring oscillator have the same cycle as that of the external clock signal, and have phases shifted from one another at an equal interval. 
     
     
       3. A phase lock loop timing generator, as recited in claim 2, wherein a delay time from a leading edge of the signal φ0 to a trailing edge of the signal φ1 is equal to 1/18 of the external clock cycle, such that an AND operation of two signals φ2 and φ6 provides a timing pulse leading with a delay of approximately 33% of the external clock cycle and having a pulse width of approximately 28% of the external clock cycle.