Shared hardware for multiply, divide, and square root exponent calculation

Abstract

The same hardware is used to implement calculations of the exponents for multiplication, division, and square root in either double or single precision. A multiplexor selects the appropriate bias value necessary for exponent computation for the given instruction type, operand precision, and output precision. A first operand multiplexor selects either the exponent of the first operand in the case of a multiplication or division instruction, and selects zero in the case of a square root instruction, since the square root operation only requires one operand. The second operand multiplexor selects the second exponent in the case of a multiplication instruction, the one's complement of the second exponent in the case of a division instruction, and the second exponent divided by two during a square root operation. Flip-flop registers latch the exponent and incremented exponent when a division or square root operation is pending. A multiplexor select between the presently calculated exponents and the saved exponents calculated for a pending division or square root operation. If the instruction scheduler has flexibility in allowing out of order instruction completion, younger multiplication instructions can be dispatched and completed during the several machine cycles during which the division/square root mantissa computation.

What is claimed is: 
     
       1. An exponent calculation circuit that computes a resultant exponent for either multiplication or a second floating point function, the exponent calculation circuit comprising: a bias selection circuit that supplies a bias that is either a multiplication bias or a second floating point function bias;   a second operand exponent selection circuit that supplies a selected second operand exponent that is either a multiplication second operand exponent or a second floating point function second operand exponent;   an exponent computation circuit that takes the selected bias, the selected second operand exponent output, and a first operand exponent as inputs and computes an operation result;   a register that stores the operation result for a second floating point function and produces a stored operation result; and   an output selection circuit that selects between the stored operation result and the operation result.   
     
     
       2. An exponent calculation circuit as in claim 1, wherein the second floating point function is division. 
     
     
       3. An exponent calculation circuit as in claim 1, wherein the second floating point function is square root. 
     
     
       4. An exponent calculation circuit as in claim 1, wherein the multiplication bias is either a single precision multiplication bias or a double precision multiplication bias. 
     
     
       5. An exponent calculation circuit as in claim 1, wherein the second floating point function bias is either a single precision second floating point function bias or a double precision floating point function bias. 
     
     
       6. A method of providing an exponent calculation circuit that computes a resultant exponent for either multiplication or a second floating point function, the method comprising the steps of: providing a bias selection circuit that supplies a bias that is either a multiplication bias or a second floating point function bias;   providing a second operand exponent selection circuit that supplies a selected second operand exponent that is either a multiplication second operand exponent or a second floating point function second operand exponent;   providing an exponent computation circuit that takes the selected bias, the selected second operand exponent output, and a first operand exponent as inputs and computes an operation result;   providing a register that stores the operation result for a second floating point function and produces a stored operation result; and   providing an output selection circuit that selects between the stored operation result and the operation result.   
     
     
       7. A method of providing an exponent calculation circuit as in claim 6, wherein the second floating point function is division. 
     
     
       8. A method of providing an exponent calculation circuit as in claim 6, wherein the second floating point function is square root. 
     
     
       9. A method of providing an exponent calculation circuit as in claim 6, wherein the multiplication bias is either a single precision multiplication bias or a double precision multiplication bias. 
     
     
       10. A method of providing an exponent calculation circuit as in claim 6, wherein the second floating point function bias is either a single precision second floating point function bias or a double precision floating point function bias. 
     
     
       11. An exponent calculation circuit that takes a first operand exponent and a second operand exponent as inputs and produces a resultant exponent as output, the exponent calculation circuit comprising: a first input exponent multiplexor that takes the first operand exponent and zero as data inputs, that takes a first input exponent multiplexor control signal as a control input, and that produces a first selected exponent as output;   a second input exponent multiplexor that takes the second operand exponent, a right-shifted second operand exponent, and a one's complement second operand exponent as data inputs, that takes a second input exponent multiplexor control signal as a control input, and that produces a second selected exponent as output;   a bias multiplexor that takes a single precision division bias, a double precision division bias, a single-to-double precision multiplication bias, a single precision multiplication bias, a double precision multiplication bias, a single precision square root bias, and a double precision square root bias as data inputs, that takes a bias multiplexor control signal as a control input, and that produces a selected bias as output;   a right shifter that takes the selected bias as data input, that takes a right shifter control signal as a control input, and that produces a right shifter selected bias, such that the right shifter selected bias is equivalent to the selected bias shifted in a less significant direction when the right shifter control signal is asserted, and such that the right shifter selected bias is equivalent to the selected bias when the right shifter control signal is deasserted;   a carry save adder that takes the right shifter selected bias, the first selected exponent, and the right shifter selected bias as inputs, and produces an exponent carry portion and an exponent sum portion as outputs; and   a conditional sum adder that takes the exponent carry portion and the exponent sum portion as inputs, and produces a non-redundant exponent and an incremented non-redundant exponent as outputs.   
     
     
       12. An exponent calculation circuit as in claim 11, further comprising: an second operand exponent inverter that takes the second operand exponent as input and produces the one's complement second operand exponent.   
     
     
       13. An exponent calculation circuit as in claim 11, wherein the right shifted second operand exponent equals the second operand exponent divided by two. 
     
     
       14. An exponent calculation circuit as in claim 11, wherein the right shifter selected bias equals the selected bias divided by two. 
     
     
       15. An exponent calculation circuit as in claim 11, further comprising: a mantissa non-overflow exponent register that takes the non-redundant exponent as data input, that takes a mantissa non-overflow exponent register control signal as a control input, and that produces a stored non-redundant exponent as output;   a mantissa overflow exponent register that takes the incremented non-redundant exponent as input, that takes a mantissa overflow exponent register control signal as a control input, and that produces a stored incremented non-redundant exponent as output;   a mantissa non-overflow exponent multiplexor that takes the non-redundant exponent and the stored non-redundant exponent as data inputs and a mantissa non-overflow multiplexor control signal as a control input, and that produces a selected non-redundant exponent as output;   a mantissa overflow exponent multiplexor that takes the incremented non-redundant exponent and the stored non-redundant exponent as data inputs and a mantissa overflow exponent multiplexor control signal as a control input, and that produces a selected incremented non-redundant exponent as output; and   an output multiplexor that takes the selected non-redundant exponent and the selected incremented non-redundant exponent as data inputs and an output multiplexor control signal as a control input, and produces the resultant exponent as output.   
     
     
       16. An exponent calculation circuit as in claim 15, wherein the first input exponent multiplexor control signal is set such that the first selected exponent is the first operand exponent, wherein the second input exponent multiplexor control signal is set such that the second selected exponent is the second operand exponent,   wherein the bias multiplexor control signal is set such that the selected bias is either the single precision multiplication bias if both operands and a floating point result are both single precision floating point numbers, the double precision multiplication bias if both operands and the floating point result are both double precision floating point numbers, or the single-to-double precision multiplication bias if both operands are single precision floating point numbers and the floating point result is a double precision floating point number,   wherein the right shifter control signal is set such that the right shifter selected bias is the selected bias,   wherein the mantissa non-overflow exponent multiplexor control signal is set such that the selected non-redundant exponent is the non-redundant exponent,   wherein the mantissa overflow exponent multiplexor control signal is set such that the selected incremented non-redundant exponent is the incremented non-redundant exponent,   wherein the output multiplexor control signal is set such that the resultant exponent is the selected non-redundant exponent when a mantissa non-overflow occurs and is the selected incremented non-redundant exponent when a mantissa overflow occurs, and   such that the resultant exponent is appropriate for a floating point multiplication operation.   
     
     
       17. An exponent calculation circuit as in claim 15, wherein the first input exponent multiplexor control signal is set such that the first selected exponent is the first operand exponent, wherein the second input exponent multiplexor control signal is set such that the second selected exponent is the one's complement second operand exponent,   wherein the bias multiplexor control signal is set such that the selected bias is either the single precision division bias if both operands and a floating point result are both single precision floating point numbers or the double precision division bias if both operands and the floating point result are both double precision floating point numbers,   wherein the right shifter control signal is set such that the right shifter selected bias is the selected bias,   wherein the mantissa non-overflow exponent register control signal is set such that the non-redundant exponent is stored in the mantissa non-overflow exponent register,   wherein the mantissa overflow exponent register control signal is set such that the incremented non-redundant exponent is stored in the mantissa overflow exponent register,   such that the stored non-redundant exponent corresponds to a mantissa non-overflow floating point division operation and the stored incremented non-redundant exponent corresponds to a mantissa overflow floating point division operation.   
     
     
       18. An exponent calculation circuit as in claim 17, wherein the mantissa non-overflow exponent multiplexor control signal is set such that the selected non-redundant exponent is the stored non-redundant exponent,   wherein the mantissa overflow exponent multiplexor control signal is set such that the selected incremented non-redundant exponent is the stored incremented non-redundant exponent,   wherein the output multiplexor control signal is set such that the resultant exponent is the selected non-redundant exponent when a mantissa non-overflow occurs and is the selected incremented non-redundant exponent when a mantissa overflow occurs, and   such that the resultant exponent is appropriate for a floating point division operation.   
     
     
       19. An exponent calculation circuit as in claim 15, wherein the first input exponent multiplexor control signal is set such that the first selected exponent is zero, wherein the second input exponent multiplexor control signal is set such that the second selected exponent is the right shifted second operand exponent,   wherein the bias multiplexor control signal is set such that the selected bias is either the single precision division bias if the second operand exponent is even and both operands and a floating point result are both single precision floating point numbers, the double precision division bias if the second operand exponent is even and both operands and the floating point result are both double precision floating point numbers, the single precision square root bias if the second operand exponent is odd and both operands and a floating point result are both single precision floating point numbers, or the double precision square root bias if both operands and the floating point result are both double precision floating point numbers,   wherein the right shifter control signal is set such that the right shifter selected bias is the selected bias shifted in a less significant direction,   wherein the mantissa non-overflow exponent register control signal is set such that the non-redundant exponent is stored in the mantissa non-overflow exponent register,   wherein the mantissa overflow exponent register control signal is set such that the incremented non-redundant exponent is stored in the mantissa overflow exponent register, and   such that the stored non-redundant exponent corresponds to a mantissa non-overflow floating point square root operation and the stored incremented non-redundant exponent corresponds to a mantissa overflow floating point square root operation.   
     
     
       20. An exponent calculation circuit as in claim 19, wherein the mantissa non-overflow exponent multiplexor control signal is set such that the selected non-redundant exponent is the stored non-redundant exponent,   wherein the mantissa overflow exponent multiplexor control signal is set such that the selected incremented non-redundant exponent is the stored incremented non-redundant exponent,   wherein the output multiplexor control signal is set such that the resultant exponent is the selected non-redundant exponent when a mantissa non-overflow occurs and is the selected incremented non-redundant exponent when a mantissa overflow occurs, and   such that the resultant exponent is appropriate for a floating point square root operation.   
     
     
       21. An exponent calculation circuit as in claim 11, further comprising: a mantissa non-overflow exponent out-of-range detector that takes the non-redundant exponent as input and produces an exponent underflow signal and an exponent overflow signal as outputs, such that the exponent underflow signal indicates that the non-redundant exponent is less than a minimum representable exponent, and such that the exponent overflow signal indicates that the non-redundant exponent is greater than a maximum representable exponent; and   a mantissa overflow exponent out-of-range detector that takes the incremented non-redundant exponent as input and produces an incremented exponent underflow signal and an incremented exponent overflow signal as outputs, such that the incremented exponent underflow signal indicates that the incremented non-redundant exponent is less than the minimum representable exponent, and such that the incremented exponent overflow signal indicates that the incremented non-redundant exponent is greater than the maximum representable exponent.   
     
     
       22. An exponent calculation circuit as in claim 11, wherein the single precision division bias is 007F, the double precision division bias is 03FF, the single-to-double precision multiplication bias is 0301, the single precision multiplication bias is is 1F81, the double precision multiplication bias is 1C01, the single precision square root bias is 0080, and the double precision square root bias is 0400. 
     
     
       23. A method of performing an exponent calculation from a first operand exponent and a second operand exponent to produce a resultant exponent, the method comprising the steps of: (a) selecting a first selected exponent from among the first operand exponent and zero;   (b) selecting a second selected exponent from among the second operand exponent, a right-shifted second operand exponent, and a one's complement second operand exponent;   (c) selecting a selected bias from among a single precision division bias, a double precision division bias, a single-to-double precision multiplication bias, a single precision multiplication bias, a double precision multiplication bias, a single precision square root bias, and a double precision square root bias;   (d) selectively shifting the selected bias to the right to produce a right shifted selected bias;   (e) adding the right shifted selected bias, the first selected exponent, and the right shifted selected bias to produce an exponent carry portion and an exponent sum portion; and   (f) adding the exponent carry portion and the exponent sum portion to produce a non-redundant exponent and an incremented non-redundant exponent.   
     
     
       24. A method of performing an exponent calculation as in claim 23 further comprising the step of: inverting the second operand exponent to produce the one's complement second operand exponent.   
     
     
       25. A method of performing an exponent calculation as in claim 23 wherein the right-shifted second operand exponent equals the second operand exponent divided by two. 
     
     
       26. A method of performing an exponent calculation as in claim 23 wherein the right shifted selected bias equals the selected bias divided by two. 
     
     
       27. A method of performing an exponent calculation as in claim 23 further comprising the steps of: (g) storing the non-redundant exponent to produce a stored non-redundant exponent;   (h) storing the incremented non-redundant exponent to produce a stored incremented non-redundant exponent;   (i) selecting between the non-redundant exponent and the stored non-redundant exponent to produce a selected non-redundant exponent;   (j) selecting between the incremented non-redundant exponent and the stored incremented non-redundant exponent to produce a selected incremented non-redundant exponent; and   (k) selecting between the selected non-redundant exponent and the selected incremented non-redundant exponent to produce the resultant exponent.   
     
     
       28. A method of performing an exponent calculation as in claim 27, wherein step (a) selects the first operand exponent,   wherein step (b) selects the second operand exponent,   wherein step (c) selects either the single precision multiplication bias if both operands and a floating point result are both single precision floating point numbers, the double precision multiplication bias if both operands and the floating point result are both double precision floating point numbers, or the single-to-double precision multiplication bias if both operands are single precision floating point numbers and the floating point result is a double precision floating point number,   wherein step (d) selects not to shift the selected bias to the right,   wherein step (i) selects the non-redundant exponent,   wherein step (j) selects the incremented non-redundant exponent,   wherein step (k) selects the selected non-redundant exponent when a mantissa non-overflow occurs and selects the selected incremented non-redundant exponent when a mantissa overflow occurs, and   such that the resultant exponent is appropriate for a floating point multiplication operation.   
     
     
       29. A method of performing an exponent calculation as in claim 27, wherein step (a) selects the first operand exponent,   wherein step (b) selects the one's complement second operand exponent,   wherein step (c) selects either the single precision division bias if both operands and a floating point result are both single precision floating point numbers or the double precision division bias if both operands and the floating point result are both double precision floating point numbers,   wherein step (d) selects not to shift the selected bias to the right, and   such that the stored non-redundant exponent corresponds to a mantissa non-overflow floating point division operation and the stored incremented non-redundant exponent corresponds to a mantissa overflow floating point division operation.   
     
     
       30. A method of performing an exponent calculation as in claim 29, wherein step (i) selects the stored non-redundant exponent,   wherein step (j) selects the stored incremented non-redundant exponent,   wherein step (k) selects the selected non-redundant exponent when a mantissa non-overflow occurs and selects the selected incremented non-redundant exponent when a mantissa overflow occurs, and   such that the resultant exponent is appropriate for a floating point division operation.   
     
     
       31. A method of performing an exponent calculation as in claim 27, wherein step (a) selects the zero,   wherein step (b) selects the right-shifted second operand exponent,   wherein step (c) selects either the single precision division bias if the second operand exponent is even and both operands and a floating point result are both single precision floating point numbers, the double precision division bias if the second operand exponent is even and both operands and the floating point result are both double precision floating point numbers, the single precision square root bias if the second operand exponent is odd and both operands and a floating point result are both single precision floating point numbers, or the double precision square root bias if both operands and the floating point result are both double precision floating point numbers,   wherein step (d) selects to shift the selected bias to the right, and   such that the stored non-redundant exponent corresponds to a mantissa non-overflow floating point square root operation and the stored incremented non-redundant exponent corresponds to a mantissa overflow floating point square root operation.   
     
     
       32. A method of performing an exponent calculation as in claim 31, wherein step (i) selects the stored non-redundant exponent,   wherein step (j) selects the stored incremented non-redundant exponent,   wherein step (k) selects the selected non-redundant exponent when a mantissa non-overflow occurs and selects the selected incremented non-redundant exponent when a mantissa overflow occurs, and   such that the resultant exponent is appropriate for a floating point square root operation.   
     
     
       33. A method of performing an exponent calculation as in claim 23 further comprising the steps of: detecting if the non-redundant exponent is less than a minimum representable exponent;   detecting if the non-redundant exponent is greater than a maximum representable exponent; and   detecting if the-incremented non-redundant exponent is less than the minimum representable exponent; and   detecting if the incremented non-redundant exponent is greater than the maximum representable exponent.   
     
     
       34. A method of performing an exponent calculation as in claim 23, wherein the single precision division bias is 007F, the double precision division bias is 03FF, the single-to-double precision multiplication bias is 0301, the single precision multiplication bias is 1F81, the double precision multiplication bias is 1C01, the single precision square root bias is 0080, and the double precision square root bias is 0400.