Method and apparatus for testing semiconductor integrated circuit devices

Abstract

A method and apparatus for testing a semiconductor integrated circuit device is described. During an aging test of the integrated circuit device, a situation, in which latch up of the semiconductor integrated circuit device can occur, is intermittently created by intermittently supplying a pulse of a power supply voltage V b , which is higher than a normal voltage V a in accordance with a rated power supply voltage of the tested integrated circuit device. The power supply to the tested semiconductor integrated circuit device is temporarily cut off when latch up occurs. If a second latch up occurs after a restart of the aging test, it is determined that there is an abnormality in the tested semiconductor integrated circuit device. The power supply to the tested semiconductor integrated circuit device is permanently cut off in response to this determination. This prevents damage to the test-object integrated semiconductor device and permits later determination of the degree to which the device is latch up immune.

What is claimed is: 
     
       1. A method for testing a semiconductor integrated circuit device, comprising the steps of: (a) supplying a power supply voltage to the semiconductor integrated circuit device;   (b) intermittently generating a latch up pulse in the power supply voltage to the semiconductor integrated circuit device;   (c) determining whether a latch up condition is present in the semiconductor integrated circuit device;   (d) temporarily cutting off the power supply voltage to the semiconductor integrated circuit device when the latch up condition is present;   (e) resupplying the power supply voltage to the semiconductor integrated circuit device;   (f) generating additional latch up pulses in the power supply voltage;   (g) determining whether additional latch up conditions are present in the semiconductor integrated circuit device within a predetermined number of the additional latch up pulses;   (h) cutting off the power supply to the semiconductor integrated circuit device when a predetermined number of additional latch up conditions are present in the predetermined number of additional latch up pulses; and   (i) repeating steps (b-h) when the additional latch up conditions do not occur in the predetermined number of latch up pulses.   
     
     
       2. The method of claim 1, wherein the latch up pulse generating step comprises generating a latch up voltage pulse having a voltage greater than a rated power supply voltage of the semiconductor integrated circuit device. 
     
     
       3. The method of claim 2, wherein the latch up pulse generating step comprises generating a latch up voltage pulse having a voltage less than a breakdown voltage of the semiconductor integrated circuit device. 
     
     
       4. The method of claim 1, wherein the determination steps each comprise the steps of: determining a normal operating current;   determining a pulse operating current; and   determining if an actual operating current of the semiconductor integrated circuit device is at least equal to a latch up current, the latch up current being not less than the pulse operating current.   
     
     
       5. The method of claim 4, wherein the normal operating current determining step comprises the steps of: determining if the actual operating current of the semiconductor integrated circuit device is between a previous normal operating current value and the latch-up current; and   resetting the normal operating current to the actual operating current when the actual operating current is between the previous normal operating current value and the latch-up current.   
     
     
       6. The method of claim 4, further comprising the step of determining discrimination current by subtracting the normal operating current from the pulse operating current, wherein latch up current is equal to the pulse operating current and the discrimination current. 
     
     
       7. The method of claim 4, further comprising the step of determining a discrimination current, wherein the discrimination current determining step comprises the steps of: subtracting the normal operating current from the pulse operating current; and   adding an offset current to the pulse operating current.   
     
     
       8. The method of claim 4, further comprising the step of determining a discrimination current, wherein the discrimination current determining step comprises: determining an average normal operating current;   determining an average pulse current; and   subtracting the average normal operating current from the average pulse current.   
     
     
       9. The method of claim 1, wherein the predetermined number of additional latch up pulses is one. 
     
     
       10. The method of claim 1, wherein the predetermined number of additional latch up conditions is at least one. 
     
     
       11. The method of claim 1, wherein the determination steps are based on a rate of increase in a power supply current after each application of the latch up pulse. 
     
     
       12. A non-destructive testing apparatus for a semiconductor integrated circuit device, comprising: a pulse power supply for supplying voltage to the semiconductor integrated circuit device;   a current measuring circuit for measuring a current flowing in the semiconductor integrated circuit device;   an abnormal condition determining circuit for determining an abnormal current condition in the semiconductor integrated circuit device based on the measured current, and for outputting a power supply cut off signal upon determining an abnormal current condition exists; and   a current limiting circuit for receiving the power supply cut off signal and for turning off the pulse power supply in response to the power supply cut off signal;   wherein the abnormal condition circuit temporarily outputs the power supply cut off signal after each of a first predetermined number of abnormal current conditions are determined and permanently outputs the power supply cut off signal after a second predetermined number of abnormal current conditions are determined, wherein the second predetermine number is greater than the first predetermined number.   
     
     
       13. The non-destructive testing apparatus of claim 12, wherein the first predetermined number is one, and the second predetermined number is two. 
     
     
       14. The non-destructive testing apparatus of claim 12, wherein the first predetermined number is at least two, and the second predetermined number is at least three. 
     
     
       15. The non-destructive testing apparatus of claim 14, wherein the second predetermined number is one greater than the first predetermined number. 
     
     
       16. The non-destructive testing apparatus of claim 12, wherein the pulse power supply generates a steady state voltage signal having a first voltage level, and a pulse voltage signal having a second voltage level greater than the first voltage level. 
     
     
       17. The non-destructive testing apparatus of claim 12, wherein the abnormal current condition determining circuit comprises: a normal operating current determining circuit for determining a first current level representative of a normal operating condition of the semiconductor integrated circuit device;   a pulse operating current determining circuit for determining a second current level representative of a pulse operating condition of the semiconductor integrated circuit;   an abnormal operating circuit current determining circuit for determining a third current level representative of a discrimination current plus the pulse operating current;   comparing means for comparing the measured current to at least one of the second and third current levels; and   power supply cut off signal generating means for generating the power supply cut off signal based on an output from the comparing means.