Method of contact planarization

Abstract

A method of planarizing an electrical contact region in a silicon substrate uses spin-on-glass or polysilicon as plug material (42) to fill a contact hole (34). A device or doped region (31) is formed at the surface of the substrate (30) and an insulating layer (33) is formed over the substrate so that the entire doped region is covered by the insulating layer. The contact hole is then formed through the insulating layer to expose a portion of the doped region. To increase the conductivity of the doped region through the contact hole, a filler layer of either spin-on-glass or polysilicon, thick enough to substantially fill the contact hole, is formed over the insulating layer. The filler layer is then etched away from the portions around the contact hole by a conventional dry or wet oxide etching process.

What is claimed is: 
     
       1. A method of planarizing an electrical contact region in a semiconductor device comprising the steps of: providing a substrate having a surface and a doped region on said surface;   forming an insulating layer over said surface of said substrate, said insulating layer covering substantially the entire doped region;   forming a hole through said insulating layer to expose at least a portion of said doped region;   filling a substantial portion of said hole with a material selected from the group consisting of spin-on-glass and polysilicon; and   forming a conducting layer over said insulating layer and said material in said hole;   before the filling step, forming a polysilicon layer over said insulating layer, a portion of said polysilicon layer extending onto said exposed portion of said doped region;   forming a metal layer over said polysilicon layer;   forming a barrier layer over said metal layer; and   thermally annealing said polysilicon layer and said metal layer to form a first metal silicide layer on said insulating layer and a second metal silicide layer on a surface of said doped region.   
     
     
       2. The method of claim 1 wherein said filling step comprises: forming a filling layer with said material, said filling layer having a first portion overlying said insulating layer and a second portion within said hole, said second portion of said filling layer having a thickness sufficient to substantially fill said hole; and   etching said filling layer so that said first portion is substantially removed from said insulating layer and said second portion substantially remains within said hole.   
     
     
       3. The method of claim 2 wherein said thickness of said filling layer within said hole remains substantially constant during said etching step. 
     
     
       4. The method of claim 2 wherein said etching step comprises a wet etching process. 
     
     
       5. The method of claim 2 wherein said etching step comprises a dry etching process. 
     
     
       6. The method of claim 2 wherein the step of forming said filling layer comprises: depositing a layer of spin-on-glass over said insulating layer and into said hole;   three-stage hot plate baking said layer of spin-on-glass at about 100° C., 200° C. and 300° C.; and   curing said layer of spin-on-glass at about 400° C.-450° C.   
     
     
       7. The method of claim 1 further including the steps of: before the filling step, forming a polysilicon layer over said insulating layer, a portion of said polysilicon layer extending onto said exposed portion of said doped region;   forming a metal layer over said polysilicon layer; and   thermally annealing said polysilicon layer and said metal layer in a nitrogen containing atmosphere to form a metal nitride layer and a metal silicide layer under Said metal nitride layer.   
     
     
       8. The method of claim 7 wherein the metal layer is titanium. 
     
     
       9. The method of claim 1 wherein said metal layer is titanium. 
     
     
       10. A method of planarizing an electrical contact region on a silicon substrate comprising the steps of: forming a doped region at the surface of said substrate;   forming an insulating layer over said surface;   forming an opening through said insulating layer to expose a portion of said doped region;   forming a polysilicon layer over said insulating layer, a portion of said polysilicon layer extending onto said portion of said doped region;   forming a titanium layer over said polysilicon layer;   thermally annealing said polysilicon layer and said titanium layer in a nitrogen containing atmosphere to form a titanium nitride layer and a titanium silicide layer under said titanium nitride layer, said thermally annealing step comprises heating said polysilicon layer and said titanium layer in an ammonia gas atmosphere between 650° C. and 800° C. for about 3.0 seconds;   filling said opening with a material selected from the group consisting of spin-on-glass and polysilicon;   forming a conducting layer to cover said titanium nitride layer and at least a portion of said filled opening.   
     
     
       11. The method of claim 10 wherein said titanium nitride layer has a first portion within said opening of said insulating layer and a second portion surrounding said opening, the filling step including the steps of: forming a filling layer with said material over said titanium nitride layer, said filling layer having a thickness sufficient to substantially fill said opening in said insulating layer; and   etching said filling layer to expose said second portion of said titanium nitride layer without exposing said first portion of said titanium nitride layer.   
     
     
       12. The method of claim 10 wherein said filling layer is a layer of spin-on-glass. 
     
     
       13. The method of claim 10 wherein said filling layer is a layer of polysilicon. 
     
     
       14. The method of claim 10 wherein said polysilicon layer has a thickness of about 1000 Å. 
     
     
       15. The method of claim 10 wherein said titanium layer has a thickness of about 500 Å. 
     
     
       16. A method of planarizing a contact region on a silicon substrate comprising the steps of: forming a doped region at the surface of said substrate;   forming an insulating layer over said surface;   forming an opening through said insulating layer to expose a portion of said doped region;   forming a polysilicon layer over said insulating layer, a portion of said polysilicon layer extending onto said portion of said doped region;   forming a titanium layer over said polysilicon layer;   forming a barrier layer over said titanium layer;   thermally annealing said titanium layer and said polysilicon layer to form a titanium silicide layer on said insulating layer;   filling at least a portion of said opening with a material selected from the group consisting of spin-on-glass and polysilicon; and   forming a conducting layer to cover said barrier layer and said filled opening, said barrier layer having a first portion within said opening of said insulating layer and a second portion surrounding said opening, the filling step comprising:   forming a filling layer with said material over said barrier layer, said filling layer having a thickness sufficient to substantially fill said opening in said insulating layer; and   oxide etching said filling layer to expose said second portion of said barrier layer without exposing said first portion of said barrier layer.   
     
     
       17. The method of claim 16 wherein said filling layer is a layer of spin-on-glass. 
     
     
       18. The method of claim 16 wherein said filling layer is a layer of polysilicon. 
     
     
       19. The method of claim 16 wherein said thermal annealing step comprises heating said titanium layer and said polysilicon layer in an ammonia gas atmosphere between 650° C. and 800° C. for about 30 seconds. 
     
     
       20. The method of claim 16 wherein said polysilicon layer has a thickness of about 500 Å to 1000 Å. 
     
     
       21. The method of claim 16 wherein said titanium layer has a thickness of about 500 Å. 
     
     
       22. The method of claim 16 wherein said barrier layer is a titanium nitride layer having a thickness of about 500 Å to 1000 Å.