Method of forming an antifuse in an integrated circuit

Abstract

An antifuse structure in an integrated circuit including a first interconnection line, a second interconnection line formed over the first interconnection line, and a plurality of programming layers between the first and second interconnection lines. Each pair of programming layers has a metal layer therebetween which dissolves with the programming layers to form a conducting link during the programming of such antifuse structure. Such antifuse structure may also include a conductive plug between the programming layers and the second interconnection line.

What is claimed is: 
     
       1. A method of forming an antifuse in an integrated circuit having a first insulating layer on a semiconductor substrate, said method comprising: forming a first interconnection layer on said first insulating layer;   forming a second insulating layer over said first metal interconnection layer;   forming an aperture through said second insulating layer where said antifuse is to be located to expose a portion of said first interconnection layer;   forming a first programming layer on said first interconnection layer;   forming a barrier metal layer in said aperture on said first programming layer;   forming a second programming layer on said barrier metal layer in said aperture; and   forming a second interconnection layer on said barrier metal layer;   whereby, upon programming said antifuse, a consistent conducting link is formed between said first and second metal interconnection layers.   
     
     
       2. The method of claims 1 wherein said first programming layer forming step is performed before said second insulating layer forming step. 
     
     
       3. The method of claim 1 wherein said first programming layer forming step is performed after said second insulating layer aperture forming step. 
     
     
       4. The method of claim 1 wherein said first and second programming layers comprise amorphous silicon. 
     
     
       5. The method of claim 1 further comprising forming an insulating spacer region on sides of said second insulating layer in said aperture and on part of said first interconnection layer portion next to said second insulating layer sides. 
     
     
       6. The method of claim 5 wherein said spacer region comprises amorphous silicon. 
     
     
       7. A method of forming an antifuse in an integrated circuit having a first insulating layer on a semiconductor substrate, said method comprising: forming a first interconnection layer on said first insulating layer;   forming a second insulating layer over said first interconnection layer, said second insulating layer having a top surface;   forming an aperture through said second insulating layer where said antifuse is to be located to expose a portion of said first interconnection layer;   forming a metal plug in said aperture, said plug contacting said first interconnection layer and having a top surface substantially coplanar with said top surface of said second insulating layer;   forming a first programming layer on said second insulating layer in contact with said top surface of said plug;   forming a first layer of barrier metal in contact with and over said first programming layer;   forming a second programming layer in contact with and over said barrier metal layer; and   forming a second metal interconnection layer in contact with and on said second programming layer;   whereby, upon programming said antifuse, a consistent conducting link is formed between said first and second metal interconnection layers.   
     
     
       8. The method of claim 7 wherein said first and second programming layers comprise amorphous silicon. 
     
     
       9. The method of claim 7 wherein said metal plug comprises a refractory metal. 
     
     
       10. The method of claim 7 wherein said metal plug comprises tungsten. 
     
     
       11. The method of claim 7 further comprising forming a second layer of barrier metal in contact with and over said plug, said barrier metal of said second layer having a viscosity so as to smooth irregularities on the top surface of said plug. 
     
     
       12. The method of claim 11 wherein said second layer of barrier metal forming step comprises sputtering a layer of titanium-tungsten with a thickness in the range of 500 to 1500 Å. 
     
     
       13. A method of forming an antifuse in an integrated circuit having a first insulating layer on a semiconductor substrate, said method comprising: forming a first interconnection layer on said first insulating layer;   forming a second insulating layer over said first interconnection layer, said second insulating layer having a top surface;   forming an aperture through said second insulating layer where said antifuse is to be located to expose a portion of said first interconnection layer;   forming a metal plug in said aperture, said plug contacting said first interconnection layer and having a top surface substantially coplanar with said top surface of said second insulating layer;   forming a layer of barrier metal in contact with and over said plug, said barrier metal having a viscosity so as to smooth irregularities on the top surface of said plug;   forming a programming layer on said second insulating layer in contact with a top surface of said barrier metal; and   forming a second metal interconnection layer in contact with and on said programming layer.   
     
     
       14. The method of claim 13 wherein said layer of barrier metal forming step comprises sputtering .a layer of titanium-tungsten with a thickness in the range of 500 to 1500 Å.