Full and empty flag generator for synchronous FIFOS

Abstract

The invention describes an asynchronous state machine with a programmable tSKEW that is used to generate an empty and full flag in a synchronous FIFO buffer. The present invention reduces the delay associated in producing the full or empty flags from a typical eight gate delays, to as little as no gate delays. The present invention accomplishes this by using a set state machine which can only make an internal flag go low, or active, and a reset state machine which can only make the internal flag go high, or inactive. The functioning of the set state machine and the reset state machine is controlled by a blocking logic. The output of each of the state machines is stored in a latch. The output of the latch is presented to an input of the blocking logic, which is used by the blocking logic to control the activity of the state machines.

We claim: 
     
       1. An apparatus for generating an output flag representing the fullness of a FIFO buffer, said apparatus comprising: a state machine having a first input receiving a write clock, a second input receiving a read clock, a third input receiving a look-ahead signal, a fourth input receiving a non look-ahead signal and a fifth input receiving free running read clock, said state machine manipulating said inputs to produce an output that is at a one logic state when said FIFO is empty and is at another logic state when said FIFO is not empty.   
     
     
       2. An apparatus for generating an output flag representing the fullness of a FIFO buffer, said apparatus comprising: a first state machine having a first input receiving a write clock, a second input receiving a first read clock and a third input receiving a look-ahead signal, said first state machine manipulating said inputs to produce a first output signal that is either at a first logic state or at a second logic state;   a second state machine having a first input receiving said write clock, a second input receiving a second read clock, a third input receiving a non look-ahead signal and a fourth input for receiving control information, said second state machine manipulating said inputs to produce a second output signal that is either at a first logic state or at a second logic state;   a latch having a first input receiving said first output signal, a second input receiving said second output signal, a third output signal equal to said first output signal and a fourth output signal signal equal to said second output signal, said latch for holding said third and fourth output signals until said first and second output signals change logic states, said fourth output signal representing an output flag that is at one logic state when said FIFO is empty and is at another logic state when said FIFO is not empty; and   logic means having a logic input receiving said third output signal of said latch and an output presenting said fourth input to said first state machine, said logic means uses said logic input to produce said control information.   
     
     
       3. The apparatus according to claim 2 wherein said empty flag is a full flag that is at one logic state when said FIFO is full and is at another logic state when said FIFO is not full. 
     
     
       4. The apparatus according to claim 2 wherein said FIFO is a synchronous FIFO. 
     
     
       5. The apparatus according to claim 2 wherein said first read clock is an enabled read clock. 
     
     
       6. The apparatus according to claim 2 wherein said write clock is an enabled write clock. 
     
     
       7. The apparatus according to claim 2 wherein said second read clock is a free running read clock. 
     
     
       8. The apparatus according to claim 2 further comprising delay means having an input receiving said write clock and an output being presented to said first input of said first state machine, said delay means provides a predetermined delay to said first input of said state machine producing a tSKEW delay in producing said output signal. 
     
     
       9. The apparatus according to claim 8 wherein said predetermined delay is determined during fabrication. 
     
     
       10. The apparatus according to claim 8 wherein said predetermined delay is programmable. 
     
     
       11. An apparatus for generating an output flag representing the fullness of a FIFO buffer, said apparatus comprising: delay means having an input receiving a write clock and a delay output, said delay means provides a predetermined delay to said delay output;   a first state machine having a first input receiving said delay output, a second input receiving a first read clock and a third input receiving a look-ahead signal, said first state machine manipulating said inputs to produce a first output that is either at a first logic state or at a second logic state;   a second state machine having a first input receiving said write clock, a second input receiving a second read clock, a third input receiving a non look-ahead signal and a fourth input for receiving control information, said state machine manipulating said inputs to produce a second output that is either at a first logic state or at a second logic state;   a latch having a first input receiving said first output, a second input receiving said second output, a third output signal equal to said first output and a fourth output signal equal to said second output, said latch for holding said second and third output signals until said first and second outputs change states, said third output signal representing an output flag that is at one logic state when said FIFO is empty and is at another logic state when said FIFO is not empty; and   logic means having an input receiving said fourth output signal of said latch and an output presenting said fourth input of said second state machine, said logic means uses said input to produce said control information.   
     
     
       12. The apparatus according to claim 11 wherein said empty flag is a full flag that is at one logic state when said FIFO is full and is at another logic state when said FIFO is not full. 
     
     
       13. The apparatus according to claim 11 wherein said FIFO is a synchronous FIFO. 
     
     
       14. The apparatus according to claim 11 wherein said first read clock is an enabled read clock. 
     
     
       15. The apparatus according to claim 11 wherein said write clock is an enabled write clock. 
     
     
       16. The apparatus according to claim 11 wherein said second read clock is a free running read clock. 
     
     
       17. The apparatus according to claim 11 wherein said predetermined delay is determined during fabrication. 
     
     
       18. The apparatus according to claim 11 wherein said predetermined delay is programmable. 
     
     
       19. The apparatus according to claim 18 wherein said predetermined delay is electronically programmable in response to an externally generated signal. 
     
     
       20. The apparatus according to claim 18 wherein said predetermined delay is programmable to a value as small a no delay.