Superconducting fault-tolerant programmable memory cell incorporating Josephson junctions

Abstract

A superconducting fault-tolerant programmable read-only memory (SFT-PROM) cell stores information in the phases of superconducting wires in a Josephson array. The information is addressable and retrievable in a fault-tolerant manner due to the non local nature of the information stored. The coding and decoding process is content-addressable and parallel due to the multitude of interconnections, resulting in picosecond data access time. The SFT-PROM cell comprises superposed WRITE/READ arrays and a reset circuit that ensures multiple non-destructive read-out of data.

What is claimed is: 
     
       1. A superconducting fault-tolerant programmable memory cell comprising: N bit lines of superconducting wires disposed in substantially parallel relation to one another;   N word lines of superconducting wires disposed in substantially parallel relation to one another, said word lines being superimposed with said bit lines and being disposed substantially orthogonally with respect to said bit lines; and   N×N nodes of Josephson junctions, a junction being formed at each of the intersections of said bit lines and said word lines, comprising a READ array to address stored information in the form of a N-bit image.   
     
     
       2. A superconducting fault-tolerant programmable memory cell as set forth in claim 1, where the stored information is stored as flux quanta. 
     
     
       3. A superconducting fault-tolerant programmable memory cell as set forth in claim 2, further comprising read-out means for non-destructively reading out data at picosecond time scale. 
     
     
       4. A superconducting fault-tolerant programmable memory cell as set forth in claim 1, further comprising a reset circuit. 
     
     
       5. A superconducting fault-tolerant programmable memory cell as set forth in claim 1, where said READ array to address stored information is content-addressable. 
     
     
       6. A superconducting fault-tolerant programmable memory cell as set forth in claim 1, where said READ array to address stored information is parallel addressable. 
     
     
       7. A superconducting fault-tolerant programmable memory cell as set forth in claim 1, further comprising a WRITE array superimposed in said READ array. 
     
     
       8. A superconducting fault-tolerant programmable memory cell as set forth in claim 7, where said WRITE array includes subcells comprising double-junction SQUID. 
     
     
       9. A superconducting fault-tolerant programmable memory cell as set forth in claim 8, further comprising a reset circuit. 
     
     
       10. A superconducting fault-tolerant programmable memory cell as set forth in claim 7, further comprising a reset circuit. 
     
     
       11. A superconducting fault-tolerant programmable memory cell comprising: N bit lines of superconducting wires disposed in substantially parallel relation to one another;   N word lines of superconducting wires disposed in substantially parallel relation to one another, said word lines being superimposed with said bit lines and being disposed substantially orthogonally with respect to said bit lines; and   N×N nodes of Josephson junctions in superconducting phase, a junction being formed at each of the intersections of said bit lines and said word lines, comprising a READ array to retrieve stored information in the form of a N-bit image.   
     
     
       12. A superconducting fault-tolerant programmable memory cell as set forth in claim 11, where the stored information is stored as flux quanta. 
     
     
       13. A superconducting fault-tolerant programmable memory cell as set forth in claim 12, further comprising read-out means for non-destructively reading out data at picosecond time scale. 
     
     
       14. A superconducting fault-tolerant programmable memory cell as set forth in claim 11, further comprising a reset circuit. 
     
     
       15. A superconducting fault-tolerant programmable memory cell as set forth in claim 11, where said READ array to retrieve stored information is content-addressable. 
     
     
       16. A superconducting fault-tolerant programmable memory cell as set forth in claim 11, where said READ array to retrieve stored information is parallel addressable. 
     
     
       17. A superconducting fault-tolerant programmable memory cell as set forth in claim 11, further comprising a WRITE array superimposed in said READ array. 
     
     
       18. A superconducting fault-tolerant programmable memory cell as set forth in claim 17, where said WRITE array includes subcells comprising double-junction SQUID. 
     
     
       19. A superconducting fault tolerant programmable memory cell as set forth in claim 18, further comprising a reset circuit. 
     
     
       20. A superconducting fault-tolerant programmable memory cell as set forth in claim 17, further comprising a reset circuit.