Dynamic bus with singular central precharge

Abstract

A dynamic bus system with a central precharge device is disclosed that utilizes a controller circuit with a one-shot generator and write synchronizing circuits in combination with logic output modules having pull-up/down devices. The issuance of the output enable (OE) signals is interlocked with the turn-off of the precharge. Thus, data is written to the dynamic bus only when the precharge device is inactive, avoiding bus collisions. The resulting circuitry not only ensures the precharging of the bus before the data write to the bus, but will allow the synchronized OE signals to be issued during the same clock phase as the precharge signal.

What is claimed is: 
     
       1. A system for a controlled write to a dynamic bus, comprising: a) a writing device, coupled to said dynamic bus for writing data to said dynamic bus;   b) a precharge device, coupled to said dynamic bus for precharging said dynamic bus; and   c) a control device, coupled to a clock input that receives a clock pulse, said precharge device, an output enable input, and said writing device; said control device for controlling both writing data to said dynamic bus and precharging said dynamic bus, including: c1) a pulse generating device, coupled to said clock input for generating a first and a second pulse of equal duration wherein said second pulse is offset in time from said first pulse, and the duration of said first pulse and said second pulse is shorter than said clock pulse;   c2) a first logic device, coupled between said pulse generating device and said precharge device for enabling said precharge device for a duration shorter than said first pulse duration; and   c3) a second logic device, coupled to said pulse generating device, said output enable input, and said writing device, for enabling writing data to said dynamic bus only when the precharge device is inactive.     
     
     
       2. The system of claim 1, wherein said first logic device generates a precharge pulse that is offset in time from said clock pulse. 
     
     
       3. The system of claim 1, wherein said writing device and said precharge device are enabled in the same clock pulse. 
     
     
       4. A method for synchronizing a controlled write to a dynamic bus with a precharging of the dynamic bus, comprising the steps of: a) inputting a clock pulse into a pulse generating device;   b) generating with said pulse generating device a first pulse and a second pulse of equal duration from said clock pulse, wherein said second pulse is offset in time from said first pulse, and the duration of said first pulse and said second pulse is shorter than said clock pulse;   c) generating a precharge pulse from said first pulse and said second pulse, wherein the duration of said precharge pulse is shorter than said first pulse;   d) enabling a precharge device for said duration of said precharge pulse;   e) generating a synchronized output enable signal from said first pulse and said second pulse; and   f) enabling a writing device with said synchronized output enable signal for writing data on said dynamic bus only when said precharge device is inactive.   
     
     
       5. The method of claim 4, wherein said precharge pulse is offset in time to said clock pulse. 
     
     
       6. The method of claim 4, wherein said writing device and said precharge device are enabled in the same clock pulse. 
     
     
       7. A system for a controlled write to a dynamic bus, comprising: a) a writing device, coupled to said dynamic bus for writing data to said dynamic bus;   b) a precharge device, coupled to said dynamic bus for precharging said dynamic bus; and   c) a control device having a first input coupled to a clock signal line and a second input coupled to an output enable signal line, and having a first output coupled to said precharge device and a second output coupled to said writing device; said control device including: c1) a first logic device, coupled between said clock input and said precharge device for enabling said precharge device for a duration shorter than said clock pulse; and   c2) a second logic device, electrically interlocked with said first logic device and coupled to said writing device for enabling writing data to said dynamic bus immediately upon turn off of said precharge device.     
     
     
       8. The system of claim 7, wherein said enabling of said precharge device, said turn off of said precharge device and said enabling writing data to said dynamic bus occur within the same clock cycle. 
     
     
       9. A system for controlled write to a dynamic bus, comprising: a) a writing device, coupled to the dynamic bus for writing data to the dynamic bus for writing data to the dynamic bus;   b) a precharge device, coupled to the dynamic bus for precharging the dynamic bus; and   c) control means for controlling the precharge device to perform precharging the dynamic bus in a single phase of a clock cycle, and for controlling the writing device to perform writing of the data to the dynamic bus during the single phase of the clock cycle, said control means having a first input coupled to a clock signal line, a second input coupled to an output enable signal line, a first output coupled to said precharge device and a second output coupled to said writing device.   
     
     
       10. The system of claim 9, wherein the control means further comprises: a) a clock input; and   b) A first logic device, coupled between the clock input and the precharge device for enabling the precharge device for a duration shorter than the single phase of the clock cycle.   
     
     
       11. The system of claim 10, wherein the control means further comprises: a second logic device, electrically interlocked with the first logic device and coupled to the writing device for enabling data to be written to the dynamic bus immediately upon turning off of the precharge device.