Status bit controlled HDLC accelerator

Abstract

A status bit controlled HDLC accelerator comprises a fully programmable CRC generation circuit, a partial data packet formatting/unformatting capability and a dual-mode register set. The HDLC accelerator includes a set of registers that can be written to and read from directly via a bus interface circuit. Moreover, these registers may be written to and read from at any time so that the state of the HDLC accelerator during a formatting or unformatting operation may be stored in mid-operation. The HDLC accelerator further includes a CRC generation circuit that can perform various checkword generation functions in response to a programmable CRC generator polynomial. In addition, programmable counters within the HDLC accelerator allow partial data packets to be processed which thereby enables formatting and unformatting data packets of all valid bit enumerations.

What is claimed is: 
     
       1. Operating in one of a first mode and second mode, an integrated circuit device performing high level data link control (HDLC) operations comprising: a dual-mode register set including a first storage element,   a second storage element, and   an HDLC formatter circuit alternatively coupled to said first and second storage elements through a data line, said HDLC formatter circuit formats a first bit stream from the first storage element during the first mode and unformats a second bit stream from the second storage element during the second mode; and     a bus interface unit coupled to said dual-mode register set, said bus interface unit at least enables data to be written into and read from the first and second storage elements.   
     
     
       2. The integrated circuit device according to claim 1, wherein during the second mode, said first storage element contains a first data packet and serially outputs said first data packet as the first bit stream during the first mode. 
     
     
       3. The integrated circuit device according to claim 2, wherein said first element includes a plurality of status bits, a first status bit of the plurality of status bits is used to select whether the integrated circuit device is to operate in one of said first and second modes. 
     
     
       4. The integrated circuit device according to claim 2, wherein the second storage element receives a HDLC frame and serially converts said HDLC frame into said second bit stream during the second mode. 
     
     
       5. The integrated circuit device according to claim 4, wherein during the second mode, said first storage element further contains an unformatted bit stream, equivalent to said second bit stream after being unformatted by said HDLC formatter circuit, and converts said unformatted bit stream into a packet identical in construction to said first data packet. 
     
     
       6. The integrated circuit device according to claim 4, wherein during the first mode, said second storage element further contains a formatted bit stream, equivalent to said first bit stream after being formatted by said HDLC formatter circuit, and converts said formatted first bit stream into a second data packet in accordance with HDLC protocol. 
     
     
       7. The integrated circuit device according to claim 2 further comprising a cyclic redundancy checkword (CRC) generation circuit coupled to said HDLC formatter circuit and said bus interface circuit, said CRC generation circuit calculates a CRC checkword used for detecting a transmission error of said first data packet. 
     
     
       8. The integrated circuit device according to claim 7, wherein said CRC generation circuit includes a CRC polynomial register that contains a binary representation of a CRC generator polynomial; and   a CRC register that calculates said CRC checkword based on said CRC generator polynomial contained in said CRC polynomial register.   
     
     
       9. The integrated circuit device according to claim 8, wherein said CRC polynomial register is programmable. 
     
     
       10. The integrated circuit device according to claim 7 further comprising a third storage element coupled to said bus interface circuit, said third storage element enables said first data packet, being a first plurality of bits in length and having less than the first plurality of bits of valid data, to be formatted by said HDLC formatter circuit. 
     
     
       11. The integrated circuit device according to claim 10, wherein said third storage element enables said second data packet, being a second plurality of bits in length and having less than the second plurality of bits of valid data, to be unformatted by said HDLC formatter circuit. 
     
     
       12. The integrated circuit device according to claim 11, wherein said third storage element enables said first data packet during the first mode, and alternatively said second data packet during the second mode, to bypass processing by said HDLC formatter circuit and said CRC generation circuit, provided said first data packet and alternatively said second data packet has a predetermined bit pattern. 
     
     
       13. The integrated circuit device according to claim 1, wherein said HDLC formatter circuit includes a first shift register coupled to said data line, said first shift register receives as input (i) said first bit stream from said first storage element during the first mode and (ii) said second bit stream from said second storage element during the second mode;   a first logic circuit coupled to said first shift register, said first logic circuit monitors said first bit stream for a predetermined bit pattern and controls HDLC formatting of said first bit stream in order to transmit a formatted first bit stream to said second storage element;   a second shift register coupled to said data line, said second shift register receives as input said second bit stream from said second storage element during the second mode; and   a second logic circuit coupled to said second shift register, said second logic circuit monitors said second bit stream for a specific bit pattern and controls HDLC unformatting of said second bit stream while propagating through said first shift register in order to transmit an unformatted second bit stream to said first storage element.   
     
     
       14. The integrated circuit device according to claim 13, wherein said second logic circuit further monitors said second bit stream for a second predetermined pattern being one from a group consisting of a frame flag and an abort flag. 
     
     
       15. Operating in one of a first mode and a second mode, an integrated circuit device performing high level data link control (HDLC) operations, comprising: HDLC format means for operating in the first mode to format a first data packet in accordance with an HDLC protocol and alternatively for operating in the second mode to unformat a second data packet in accordance with the HDLC protocol, including first storage means for storing said first data packet and for serially outputting said first data packet as a first bit stream during the first mode,   second storage means for storing an HDLC frame and for serially converting said HDLC frame into a second bit stream during the second mode, and   a HDLC formatting means for formatting said first bit stream during the first mode and for unformatting said second bit stream during the second mode, said HDLC formatting means being alternatively coupled to said first storage means and said second storage means; and     bus interface means for enabling a first data packet to be written to said first storage means and a second data packet to be read from said second storage means, said bus interface means being coupled to said first storage means, said second storage means, and said HDLC formatting means.   
     
     
       16. The integrated circuit device according to claim 15, wherein during the second mode, said first storage means further temporarily stores an unformatted bit stream, equivalent to said second bit stream after being unformatted by said HDLC formatting means, and converts said unformatted bit stream into a packet identical in construction to said first data packet. 
     
     
       17. The integrated circuit device according to claim 16, wherein during the first mode, said second storage means further temporarily stores a formatted bit stream, equivalent to said first bit stream after being formatted by said HDLC formatting means and converts said formatted bit stream into a packet identical in construction to said second data packet. 
     
     
       18. The integrated circuit device according to claim 15, wherein said HDLC formatting means includes first circuit means for monitoring said first bit stream to detect a predetermined bit pattern and for controlling HDLC formatting of said first bit stream in order to transmit a formatted first bit stream to said second storage means, said first circuit means being coupled to said data line; and   second circuit means for monitoring said second bit stream for a specific bit pattern and for controlling HDLC unformatting of said second bit stream propagating through said first circuit means in order to transmit an unformatted second bit stream to said first storage means, said second circuit means being coupled to said data line and said first circuit means.   
     
     
       19. The integrated circuit device according to claim 18, wherein said first circuit means of said HDLC formatting means includes first shifting means for receiving as input said first bit stream from said first storage means during the first mode and said second bit stream from said second storage means during the second mode, said first shifting means including a plurality of flip-flops cascaded in series, said first shifting means being coupled to said data line;   combinatorial logic means for performing HDLC formatting; and   first logic means for monitoring output terminals of a preselected number of said plurality of flip flops and for controlling said combinational logic means.   
     
     
       20. The integrated circuit device according to claim 18, wherein said first circuit means of said HDLC formatting means includes second shifting means for receiving as input said second bit stream from said second storage means during the second mode, said second shifting means including a plurality of flip-flops cascaded in series;   said combinatorial logic means for performing HDLC unformatting; and   second logic means for monitoring output terminals of said plurality of flip flops and controlling said combinational logic means.   
     
     
       21. The integrated circuit device according to claim 15 further comprising cyclic redundancy checkword (CRC) generation means, for calculating a CRC checkword used for detecting a transmission error of an HDLC frame and for storing a binary representation of a CRC generator polynomial, said CRC generation means being coupled to said HDLC formatting means and said bus interface means. 
     
     
       22. The integrated circuit device according to claim 21 further comprising third storage means for enabling said first data packet, being "n" bits in length and having less than "n" bits of valid data, to be formatted by said HDLC formatting means, said third storage means being coupled to said bus interface means. 
     
     
       23. The integrated circuit device according to claim 22, wherein said third storage means further enables said second data packet, being "m" bits in length and having less than "m" bits of valid data, to be unformatted by said HDLC formatting means. 
     
     
       24. A signal processing system of a first computing source being able to support bi-directional communications between the first computing source and a second computing source remotely located from the first computing system, the signal processing system comprising: a bus;   a bus interface coupled to said bus, said bus interface receives a first digital data packet to be encoded and alternatively outputs a second digital data packet after being decoded;   an analog front end interface coupled to said bus;   a processing unit coupled to said bus; and   an high level data link control (HDLC) accelerator coupled to said bus, said HDLC accelerator including a dual-mode register set operating in a first mode to encode said first digital data packet into a first HDLC frame, and alternatively, operating in a second mode to decode said second digital data packet from a second HDLC frame, and   an interface circuit coupled to said dual-mode register set, said interface circuit enables said first digital data packet to be written into said dual-mode register set and said second digital data packet to be read from said dual-mode register set.     
     
     
       25. A signal processing system of a first computing source being able to support bi-directional communications between the first computing source and a second computing source remotely located from the first computing system, said signal processing system comprising: bus means for transmitting information;   bus interface means for receiving a first digital data packet to be encoded, and alternatively for outputting a second digital data packet after being decoded;   an analog front end interface coupled to said bust;   a processing unit coupled to said bus; and   high level data link control (HDLC) accelerator means for encoding said first digital data packet and alternatively for decoding said second digital data packet, said HDLC accelerator means being coupled to said bus means and including dual-mode formatting means for operating in a first mode to encode said first digital data packet into a first HDLC frame and alternatively, for operating in a second mode to decode said second digital data packet from a second HDLC frame, and   an interface circuit, coupled to said dual-mode formatting means, for enabling said first digital data packet to be written into said dual-mode register set and said second digital data packet to be read from said dual-mode formatting means.     
     
     
       26. A method performing high level data link control (HDLC) formatting and unformatting operations, the method comprising the steps of: (1) performing said HDLC formatting operation on a first data packet during a first mode, said HDLC formatting operation includes the steps of: temporarily storing said first data packet in a first storage element,   serially shifting said first data packet as a first bit stream into an HDLC formatting circuit,   formatting said first bit stream, and   serially shifting said formatted first bit stream into a second storage element for subsequent inclusion in an HDLC frame; and     (2) performing said HDLC unformatting operation on a second data packet during a second mode, said HDLC unformatting operation includes the steps of: temporarily storing said second data packet in said second storage element,   serially shifting said second data packet as a second bit stream into said HDLC formatting circuit,   unformatting said second bit stream, and   serially shifting said unformatted second bit stream into said first storage element for subsequent inclusion in an HDLC frame.