Sense amplifier with pre-charge circuit and low-voltage operation mode

Abstract

Low-voltage-correcting bias circuitry for a sense amplifier includes first, second and third N-channel transistors. The channel of the first transistor couples a current mirror to the input terminal of the amplifier and the gate of the second transistor, the channel of the second transistor couples the gate of the first transistor to a reference terminal. The channel of the third transistor couples the supply voltage to the gate of the first transistor. The gate of the third transistor is coupled to a reference voltage. A P-channel transistor has a channel coupling the supply voltage to the gate of the first transistor. The gate of the P-channel transistor is coupled to a low-voltage-sensing signal. Pre-charge circuitry includes a nonvolatile memory cell and fourth, fifth and sixth N-channel transistors. The channel of the fourth transistor is in series with the channel of the memory cell. The channel of the fifth transistor couples the channel of the memory cell to the input of the sense amplifier. The gates of the fourth and fifth transistors are coupled to a pre-charge operation control signal. The channel of the sixth transistor couples the supply voltage to the channel of the fourth transistor and the gate of the sixth transistor is coupled to the gate of the first transistor.

We claim: 
     
       1. Low voltage correcting bias circuitry for use in a sense amplifier, said sense amplifier having an input terminal connected to the source-drain path of at least one nonvolatile memory cell, said bias circuitry comprising: a first N-channel transistor having a gate and a source-drain path, one end of said source-drain path of said first N-channel transistor coupled to said input terminal of said sense amplifier, the other end of said first N-channel transistor coupled to current mirror;   a second N-channel transistor having a gate and a source-drain path, said gate of said second transistor coupled to said input terminal of said sense amplifier, one end of said source-drain path of said second transistor coupled to a reference terminal, the other end of said source-drain path of said second transistor coupled to said gate of said first transistor;   a third N-channel transistor having a gate and a source-drain path, said gate of said third transistor coupled to first reference voltage, one end of said source-drain path of said third transistor coupled to said gate of said first transistor, the other end of said source-drain path of said third transistor coupled to a supply voltage; and   a P-channel transistor having a gate and a source-drain path, said gate of said P-channel transistor coupled to a low-voltage signal terminal, one end of said source-drain path of said P-channel transistor coupled to said supply voltage, the other end of said source-drain path of said P-channel transistor coupled to said gate of said first transistor.   
     
     
       2. The bias circuitry of claim 1, further including a capacitor connected between said gate of said P-channel transistor and said supply voltage. 
     
     
       3. The bias circuitry of claim 1, further including a fourth N-channel transistor having a gate and a source-drain path, said gate of said fourth N-channel transistor coupled to an enabling signal and said source-drain path of said fourth N-channel transistor coupling said other end of said source-drain path of said first N-channel transistor to said gate of said second transistor. 
     
     
       4. The bias circuitry of claim 1, further including a capacitor coupled between said gate of said third N-channel transistor and said reference terminal. 
     
     
       5. Pre-charge circuitry for use in a sense amplifier, said sense amplifier having an input terminal connected to the source-drain path of at least a first memory cell, said pre-charge circuitry comprising: a second memory cell having a source-drain path, one end of said source drain path of said second memory cell coupled to a reference terminal;   a first N-channel transistor having a gate and a source-drain path, said source-drain path of said first N-channel transistor coupled to pre-charge operation indicating signal, one end of said source-drain path of said first N-channel transistor coupled to the other end of said source-drain path of said second memory cell;   a second N-channel transistor having a gate and a source-drain path, said gate of said second N-channel transistor coupled to said gate of said first N-channel transistor, one end of said source drain path of said first N-channel transistor coupled to said other end of said source-drain path of said first N-channel transistor, the other end of said source-drain path of said second N-channel transistor coupled to said input of said sense amplifier;   a third N-channel transistor having a gate and a source-drain path, one end of said source-drain path of said third N-channel transistor coupled to said other end of said source-drain path of said first N-channel transistor, the other end of said source-drain path of said third N-channel transistor coupled to said supply voltage; and   a P-channel transistor having a gate and a source-drain path, said gate of said P-channel transistor coupled to a low-voltage signal terminal, one end of said source-drain path of said P-channel transistor coupled to said supply voltage, the other end of said source-drain path of said P-channel transistor coupled to said gate of said third transistor.   
     
     
       6. The pre-charge circuitry of claim 5, further including a capacitor connected between said gate of said P-channel transistor and said supply voltage.