Interconnection resource assignment method for differential current switch nets

Abstract

A method for assigning interconnection resources to input/output connection points on differential current switch logic elements which need to use the resources, but which introduce an order dependency to the assignment problem, due to restrictions unique to differential current logic. The input/output connection points are paired first as are the interconnection resources. Pairing removes the order dependency. An assignment is then made through the use of an optimizing linear assignment algorithm suitable for single input/output connection point to single interconnection resource assignments. Preferably, a cost matrix is generated to determine the optimum assignment by minimizing the total assignment cost. The paired assignments are then broken apart to assign each individual member of the point pair to an individual member of the assigned resource pair. The final assignment of the individual pair members is compared to legality constraints, the violation of which may have been masked in the calculation of assignment costs of the pairs.

Thus, having described the invention, what is claimed is: 
     
       1. An interconnection resource assignment method for assigning interconnection resources to input/output connection points on differential current switch logic elements comprising the steps of: (a) identifying all differential current switch input/output connection points requiring interconnection;   (b) pairing the identified differential current switch input/output connection points;   (c) representing the paired differential current switch input/output connection points as a single point;   (d) identifying available interconnection resources;   (e) pairing the identified interconnection resources by pairing a first interconnection resource with a second interconnection resource located within a predetermined distance from the first interconnection resource, and then repeating the same pairing procedure until each interconnection resource has been paired with another interconnection resource;   (f) representing the paired interconnection resources as a single resource;   (g) assigning each input/output connection point representing a point pair to a corresponding interconnection resource representing a resource pair according to an optimizing assignment algorithm suitable for single input/output connection point to single interconnection resource assignments; and   (h) assigning each individual interconnection resource in a pair to a specific one of the input/output connection points in the corresponding assigned point pair.   
     
     
       2. An interconnection resource assignment method according to claim 1 wherein the interconnection resources comprise interconnection pins for connecting the differential current switch logic elements to a wiring layer. 
     
     
       3. An interconnection resource assignment method according to claim 2 wherein step (g) comprises computing a single cost for assigning each input/output connection point pair to each potential interconnection pin pair and then using a linear assignment algorithm to assign input/output connection point pairs to corresponding interconnection pin pairs to minimize the sum of the assignment costs. 
     
     
       4. An interconnection resource assignment method according to claim 3 wherein the assignment cost includes a factor corresponding to a calculated distance from the input/output connection point pair to the interconnection pin pair. 
     
     
       5. An interconnection resource assignment method according to claim 4 wherein the distance from the input/output connection point pair to the interconnection pin pair is calculated as the average of the distance from a first connection point of the point pair to a first pin of the pin pair and the distance from a second connection point of the point pair to a second pin of the pin pair. 
     
     
       6. An interconnection resource assignment method according to claim 4 wherein the assignment cost is set high enough to preclude assignment whenever the distance from the input/output connection point pair to the interconnection pin pair is greater than a predetermined maximum distance or less than a predetermined minimum distance. 
     
     
       7. An interconnection resource assignment method according to claim 2 wherein step (h) comprises assigning each individual interconnection pin in a pair to a specific one of the input/output connection points in the corresponding assigned point pair such that predetermined legality constraints are met. 
     
     
       8. An interconnection resource assignment method according to claim 7 wherein step (h) comprises assigning a first interconnection pin in a pin pair to a first input/output connection point in the corresponding assigned point pair, thereby defining a first pin to point distance, and assigning a second interconnection pin in the pin pair to a second input/output connection point in the corresponding assigned point pair, thereby defining a second pin to point distance, the assignment being made such that the difference between the first pin to point distance and the second pin to point distance is less than a predetermined limit. 
     
     
       9. An interconnection resource assignment method according to claim 1 wherein the differential current switch logic elements are located on a chip on a thin film layer overlying a ceramic wiring layer, and the interconnection resources comprise hybrid interconnection pins extending from the ceramic wiring layer to the thin film layer. 
     
     
       10. An interconnection resource assignment method according to claim 9 wherein step (g) comprises computing a single cost for assigning each input/output connection point pair to each potential interconnection pin pair and then using a linear assignment algorithm to assign input/output connection point pairs to corresponding interconnection pin pairs to minimize the sum of the assignment costs. 
     
     
       11. An interconnection resource assignment method according to claim 10 wherein the assignment cost includes a factor corresponding to a calculated distance on the thin film layer from the input/output connection point pair to the interconnection pin pair. 
     
     
       12. An interconnection resource assignment method according to claim 11 wherein the assignment cost is set high enough to preclude assignment whenever the distance on the thin film layer from the input/output connection point pair to the interconnection pin pair is greater than a predetermined maximum distance or less than a predetermined minimum distance. 
     
     
       13. An interconnection resource assignment method according to claim 10 wherein the thin film layer overlies a plurality of ceramic wiring layers and the assignment cost includes a factor corresponding to the depth of the hybrid pin required to reach a desired wiring layer. 
     
     
       14. An interconnection resource assignment method according to claim 1 wherein the interconnection resources comprise wiring tracks suitable for differential current switch wiring. 
     
     
       15. An interconnection resource assignment method according to claim 14 wherein step (e) comprises pairing a first wiring track with a second wiring track having a length that differs from the first wiring track by no more than a predetermined amount, and then repeating the pairing until all wiring tracks have been paired. 
     
     
       16. An interconnection resource assignment method according to claim 14 wherein step (e) comprises pairing a first wiring track with a second wiring track located within a predetermined distance from the first wiring track at each point along its length, and then repeating the pairing until all wiring tracks have been paired. 
     
     
       17. An interconnection resource assignment method according to claim 14 wherein step (g) comprises assigning each input/output connection point representing a point pair to a corresponding wiring track representing a wiring track pair according to a routing algorithm. 
     
     
       18. An interconnection resource assignment method for assigning interconnection pins to input/output connection points on differential current switch logic elements comprising the steps of: (a) identifying all differential current switch input/output connection points requiring interconnection pins;   (b) pairing the identified differential current switch input/output connection points;   (c) representing the paired differential current switch input/output connection points as a single point;   (d) identifying suitable interconnection pins;   (e) pairing the identified interconnection pins;   (f) representing the paired interconnection pins as a single pin;   (g) computing a cost for assigning each input/output connection point pair to each interconnection pin pair;   (h) constructing a two dimensional pin to point cost matrix;   (i) assigning each input/output connection point representing a point pair to a corresponding interconnection pin representing a pin pair by using the hungarian algorithm for linear assignment on the cost matrix to minimize the total assignment cost; and   (j) assigning each interconnection pin in a pin pair to one of the input/output connection points in the corresponding assigned point pair such that predetermined legality constraints are satisfied.   
     
     
       19. An interconnection resource assignment method for assigning interconnection resources, composed of interconnection pins and wiring tracks, to input/output connection points on differential current switch logic elements comprising the steps of: (a) first assigning interconnection pins to input/output connection points on differential current switch logic elements by performing the steps of: (i) identifying differential current switch input/output connection points requiring interconnection;   (ii) pairing the identified differential current switch input/output connection points;   (iii) representing the paired differential current switch input/output connection points as a single point;   (iv) identifying available interconnection pins;   (v) pairing the identified interconnection pins;   (vi) representing the paired interconnection pins as a single pin;   (vii) assigning each input/output connection point representing a point pair to a corresponding interconnection pin representing a pin pair according to an optimizing assignment algorithm suitable for single input/output connection point to single interconnection pin assignments; and     (b) after assigning all input/output connection point pairs to interconnection pin pairs, assigning a pair of wiring tracks from each point pair to its assigned pin pair.