Data encryption control system

Abstract

The data encryption system includes a first stage and a second stage data encryption engine in combination with a micro control system. The data encryption system is responsive to control signals from the micro control system. The first stage is comprised of an 8-bit bus input and output from the first stage to the second stage data encryption engine of 64-bits. The input bus of the first stage is gated to a plurality of 8-bit registers through a plurality of AND gates having a respective one of the AND gate inputs in communication with the 8-bit bus and output from the respective AND gate directed to a respective input of the respective 8-bit registers for selectively gating data from the 8-bit bus to respective ones of the 8-bit registers. A demultiplexer includes a plurality of inputs and a plurality of outputs, a respective output of the demultiplexer being in communication with the input of a respective one of the AND gates for selectively enabling a respective one of the AND gate in response to the state of the control signals.

What is claimed is: 
     
       1. An improved data encryption system having a second stage data encryption engine of N-bits data input in combination with a microcontrol system, wherein said data encryption system is in electrical communication with said microcontrol system for receiving control signals from said microcontrol system and wherein the improvement comprises a first stage including: an M-bit bus input and an output from said first stage to said second stage data encryption engine of N-bits, wherein M is less than N but greater that 1;   register means for storing M-bits of input data at a time and accumulating N-bits of data therefrom; and   means for sequentially enabling said register means for receiving M-bits of data at a time in response to control signals from said microcontrol system.   
     
     
       2. An improved data encryption system as claimed in claim 1 further comprising means for checking the parity of data accumulated in said register means and enabling data transfer to said second stage when the parity check is complete. 
     
     
       3. An improved data encryption system as claimed in claim 2 further comprising means for signaling said microcontrol system when said data accumulated in said first stage is transferred to said second stage and resetting said first stage to receive new data bits. 
     
     
       4. An improved data encryption system having a 64-bits second stage data encryption engine in combination with a microcontrol system, wherein said data encryption system is in electrical communication with said microcontrol system for receiving control signals from said microcontrol system and wherein the improvement comprises a first stage including: an 8-bit bus input and 64-bits output from said first stage to said second stage data encryption engine;   a plurality of 8-bit registers;   a plurality of AND gates having a respective input in communication with said 8-bit bus and respective output from each of said AND gate directed to a respective input of one of said 8-bit registers for selectively gating data from said 8-bit bus to respective ones of said 8-bit registers;   a demultiplexer having a plurality of inputs and a plurality of outputs, a respective one of said outputs of said demultiplexer being in communication with said input of a respective one of said AND gates for selectively enabling a respective one of said AND gates in response to the state of said control signals.   
     
     
       5. An improved data encryption system as claimed in claim 2 further comprising means for latching data respectively into said respective registers subsequent to said data being written in said respective 8-bit register. 
     
     
       6. An improved data encryption system as claimed in claim 5 further comprising means for checking the parity of data accumulated in said registers and enabling data transfer to said second stage when the parity check is complete. 
     
     
       7. An improved data encryption system having a second stage data encryption engine of N-bits data input in combination with a microcontrol system, wherein said data encryption system is in electrical communication with said microcontrol system for receiving to control signals from said micro control system and wherein the improvement comprises a first stage including: an M-bit bus input and an output from said first stage to said second stage data encryption engine of N-bits, wherein M is less than N but greater that 1;   register means for storing M-bits of input data at a time and accumulating N-bits of data wherein N=C×M; C=2, 4, 8, 64, 128, 256; and   means for sequentially enabling said register means for receiving M-bits of data at a time in response to said control signals from said microcontrol system.   
     
     
       8. An improved data encryption system as claimed in claim 7 wherein said register means comprises: a M-bit bus;   a plurality of M-bit registers;   a plurality of gate means having respective inputs in communication with said M-bit bus and respective output to a respective one of said M-bit registers for selectively gating data on said M-bit bus to respective ones of said M-bit registers in response to said control signals from said microcontrol system.   
     
     
       9. An improved data encryption system as claimed in claim 8 further comprising means for checking the parity of data accumulated in said register means and enabling data transfer to said second stage when the parity check is complete. 
     
     
       10. An improved data encryption system as claimed in claim 9 further comprising means for signaling said microcontrol system when said data accumulated in said first stage is transferred to said second stage and resetting said first stage. 
     
     
       11. An improved data encryption system as claimed in claim 10 wherein said microcontrol system is comprised of a programmable microprocessor in bus communication with a plurality of memory units and an ASIC wherein said improved data encryption system is one of a plurality of modules of said ASIC, said ASIC having an address decoder module means for generating said control signal in response to an address generated by said microprocessor whereby data then placed on said data bus by said microprocessor is written to said register which has been enabled by said control signal. 
     
     
       12. An improved data encryption system as claimed in claim 7 further comprising means for latching said data into said respective M-bit registers subsequent to said data being written in said respective M-bit registers. 
     
     
       13. An improved data encryption system as claimed in claim 7 further comprising means for checking the parity of data accumulated in said register means and enabling data transfer to said second stage when the parity check is complete. 
     
     
       14. An improved data encryption system as claimed in claim 13 further comprising means for signaling said microcontrol system when said data accumulated in said first stage is transferred to said second stage and resetting said first stage.