Method for manufacturing a semiconductor device having reduced resistance of diffusion layers and gate electrodes

Abstract

In a method for manufacturing a semiconductor device, metal ions are doped into the surface regions of diffusion layers or a diffusion layer forming region, thereby forming metal silicide layers of low resistance on only the diffusion layers. In a further method for manufacturing a semiconductor device, metal ions are doped into the surface regions of diffusion layers or a diffusion layer forming region and the upper surface of a gate electrode. Then, the structure is subjected to a process to make a silicide, thereby forming metal silicide layers of low resistance on only the diffusion layers and the gate electrode.

What is claimed is: 
     
       1. A method for manufacturing a semiconductor device comprising the steps of: doping metal ions into a selected region in a silicon substrate having a first conductivity type so that a peak metal ion impurity concentration is present at a depth less than 500 Angstroms from the surface of said substrate;   heat treating the metal ion doped substrate at 500° C. or more in an oxygen-free atmosphere, thereby forming a silicide layer in the selected region doped with said metal ions;   doping an impurity having a second conductivity type into said silicide layer formed in the selected region; and   heat treating the substrate at 600° C. or more, thereby forming a diffusion layer of the impurity having the second conductivity type which extends to a depth from the surface of the substrate greater than the depth of said silicide layer.   
     
     
       2. The method according to claim 1, wherein said metal ions used for forming said ion doped regions are metal ions selected from the group consisting of molybdenum, tungsten, nickel, platinum, palladium, and tantalum. 
     
     
       3. The method according to claim 1, wherein said metal ions used for forming said selected region doped with metal ions are implanted with an acceleration voltage of about 50 KeV. 
     
     
       4. A method for manufacturing a semiconductor device comprising the steps of: forming at least one element separation region on a silicon substrate having a first conductivity type;   forming at least one MOSFET gate electrode on said substrate;   doping metal ions into said substrate at a selected region using the at least one element separation region and the at least one gate electrode as a mask and doping metal ions into said at least one gate electrode so a peak metal ion impurity concentration is present at a depth less than 500 Angstroms from the surface of said substrate and the surface of said gate electrode;   heat treating the metal ion doped substrate and the at least one gate electrode at 500° C. or more in an oxygen-free atmosphere, thereby forming a silicide layer in the selected region doped in the substrate and in the at least one gate electrode;   doping an impurity having a second conductivity type into the silicide layer of the selected region using the at least one element separation region and the at least one gate electrode as a mask;   heat treating the substrate and the at least one gate electrode at 600° C. or more thereby forming at least one diffusion layer of the impurity having a second conductivity type within the selected region, which extends to a depth from the surface of the substrate greater than the depth of said silicide layer; and   forming at least one wiring layer on the surface of said silicide layer.   
     
     
       5. The method according to claim 4, wherein said metal ions used in said metal ion doping steps are metal ions selected from the group consisting of molybdenum, tungsten, nickel, platinum, palladium, and tantalum. 
     
     
       6. The method according to claim 4, wherein said metal ions used for forming said selected region doped with metal ions are implanted with an acceleration voltage of about 50 KeV. 
     
     
       7. The method according to claim 4, wherein the silicide layer formed in the selected region and in the at least one gate electrode has a sheet resistance of about 1 Ohm/. 
     
     
       8. A method for manufacturing a semiconductor device comprising the steps of: doping metal ions into a selected region in a silicon substrate having a first conductivity type so that a peak metal ion impurity concentration is present at a depth less than 500 Angstroms from the surface of said substrate;   doping an impurity having a second conductivity type into the selected region doped with said metal ions;   heat treating the substrate at 500° C. or more in an oxygen-free atmosphere, thereby forming a silicide layer in the selected region doped with said metal ions, and forming a diffusion layer of said impurity having the second conductivity type which extends to a depth from the surface of the substrate greater than the depth of said silicide layer; and   forming a wiring layer on said silicide layer.   
     
     
       9. The method according to claim 8, wherein said metal ions used in said metal ion doping steps are metal ions selected from the group consisting of molybdenum, tungsten, nickel, platinum, palladium, and tantalum. 
     
     
       10. The method according to claim 8, wherein said metal ions used for forming said selected region doped with metal ions are implanted with an acceleration voltage of about 50 KeV. 
     
     
       11. A method for manufacturing a semiconductor device comprising the steps of: forming at least one element separation region on a silicon substrate having a first conductivity type;   forming at least one MOSFET gate electrode on said substrate;   using said at least one element separation region and said at least one gate electrode as a mask for doping metal ions into a selected region in said substrate and doping metal ions into said at least one gate electrode so the peak metal ion impurity concentration is present at a depth less than 500 Angstroms from the surface of said substrate;   doping an impurity having a second conductivity type into the metal ion doped selected region of said substrate using the at least one element separation region and the at least one gate electrode as a mask;   heat treating the substrate at 500° C. or more in an oxygen-free atmosphere, thereby forming a silicide layer in the selected region doped with said metal ions, and forming at least one diffusion layer of the impurity having the second conductivity type within the selected region, which extends to a depth from the surface of the substrate greater than the depth of said silicide layer; and   forming a wiring layer on the surface of said silicide layer formed in the selected region.   
     
     
       12. The method according to claim 11, wherein said metal ions used in said metal ion doping steps are metal ions selected from the group consisting of molybdenum, tungsten, nickel, platinum, palladium, and tantalum. 
     
     
       13. The method according to claim 11, wherein said metal ions used for forming said selected region doped with metal ions are implanted with an acceleration voltage of about 50 KeV. 
     
     
       14. The method according to claim 11, wherein the silicide layer formed in the selected region and in the at least one gate electrode has a sheet resistance of about 1 Ohm/. 
     
     
       15. A method for manufacturing a semiconductor device comprising the steps of: diffusing an impurity having a first conductivity type into a selected first region in a silicon substrate having a second conductivity type, thereby forming at least one diffusion layer of the first conductivity type;   doping metal ions into a selected second region in said at least one diffusion layer so that the peak concentration of the metal ions is present at a depth less than 500 Angstroms from the surface of said substrate; and   heat treating the substrate at 600° C. or more in an oxygen-free atmosphere, thereby forming a silicide layer in the selected second region doped with said metal ions, which extends to a depth from the surface of the substrate less than the depth of said at least one diffusion layer.   
     
     
       16. The method according to claim 15, wherein said metal ions used in said metal ion doping steps are metal ions selected from the group consisting of molybdenum, tungsten, nickel, platinum, palladium, and tantalum. 
     
     
       17. The method according to claim 15, wherein said metal ions used for forming said selected second region doped with metal ions are implanted with an acceleration voltage of about 50 KeV. 
     
     
       18. A method for manufacturing a semiconductor device comprising the steps of: forming at least one element separation region on a silicon substrate, the substrate having a first conductivity type;   forming at least one gate electrode of a MOSFET on said substrate;   using said at least one element separation region and said at least one gate electrode as a mask, doping an impurity having a second conductivity type into a selected first region in said substrate, thereby forming at least one diffusion layer;   doping metal ions into a selected second region using the at least one element separation region and the at least one gate electrode as a mask, the selected second region being within said at least one diffusion layer, and doping metal ions into the at least one gate electrode so that the peak impurity concentration of the metal ions is present at a depth less than 500 Angstroms from the surface of said substrate; and   heat treating the substrate at 600° C. or more in an oxygen-free atmosphere, thereby forming a silicide layer from the selected second region doped with said metal ions which is located at a depth from the surface of the substrate less than the depth of said at least one diffusion layer, and forming a silicide layer in said at least one gate electrode.   
     
     
       19. The method according to claim 18, wherein said metal ions used in said metal ion doping steps are metal ions selected from the group consisting of molybdenum, tungsten, nickel, platinum, palladium, and tantalum. 
     
     
       20. The method according to claim 18, wherein said metal ions used for forming said selected second region doped with metal ions are implanted with an acceleration voltage of about 50 KeV. 
     
     
       21. The method according to claim 18, wherein the silicide layer formed in the selected second region and in the at least one gate electrode has a sheet resistance of about 1 Ohm/. 
     
     
       22. A method of manufacturing a semiconductor device, the method comprising the steps of: preparing a silicon semiconductor body of a first conductivity type;   selectively doping metal ions into selected regions of said semiconductor body;   heat treating the metal doped substrate to form silicide layers in said selected regions;   selectively doping an impurity of a second conductivity type into said silicide layers; and   heat treating the second impurity doped substrate at 500° C. or more in an oxygen-free atmosphere to form diffusion layers of the impurity of the second conductivity type.   
     
     
       23. A method of manufacturing a semiconductor device, the method comprising the steps of: preparing a silicon semiconductor body of a first conductivity type;   forming element separation regions in the semiconductor body;   forming gate electrodes on said semiconductor body;   selectively doping metal ions into selected regions of said semiconductor body and into said gate electrodes;   heat treating the metal doped semiconductor body to form silicide layers in said selected regions and said gate electrodes;   selectively doping an impurity of a second conductivity type into the silicide layers in said selected regions;   heat treating the second impurity of the second conductivity doped semiconductor body at 500° C. or more in an oxygen free atmosphere to form source and drain diffusion layers having the second conductivity type; and   forming a wiring layer in contact with the silicide layers in said selected regions.