Low standby power redundancy circuit

Abstract

A low power redundancy circuit that has applications in CMOS memories. This circuit employs fuses to select addressing paths and to provide address information of failing memory columns. Path selection is made by rendering a fuse device non-conductive which disconnects a clamping off bias that inhibits conduction through an N-channel transistor and preventing signal flow through the selected addressing paths to the output. Memory column addressing information is generated by selectively rendering a second set of fuses conductive or non-conductive to produce a logical one or zero respectively at the output of the addressing paths. A redundant signal is used to precondition the select circuitry and prevent a transient pulse from propagating through the output of the select circuitry when a section is not activated. The circuit uses CMOS N-channel transistors configured such as to produce low standby power while being able to deliver necessary output signals when path selection is made. Portions of the redundant circuit paths are shared with other paths to further minimize the use of power.

What is claimed is: 
     
       1. A low standby power redundancy circuit for CMOS memories comprising: (a) a plurality of circuit paths arranged in parallel and having at least two sections of paths,   (b) each section of paths consisting of multiple addressing paths connected to an output of a select circuit,   (c) each section of paths maintained in low standby power state when not activated or selected,   (d) said select circuit being activated by rendering a first fuse device in said select circuit non-conductive,   (e) signal means to select each section when fuse device is rendered non-conductive and producing a signal at select circuit output,   (f) said select circuit output connected to a set of multiple addressing paths,   (g) each addressing path containing a second fuse device connected in series with the output of the select circuit,   (h) said second fuse device when rendered conductive or non-conductive providing the value of a bit in the address of a failing memory location.   
     
     
       2. The circuit of claim 1 wherein said select circuit maintains circuitry in low standby power state comprising: (a) an output transistor connected between a gating transistor to circuit ground and one or more biasing transistors to Vcc,   (b) the input to said gating transistor connected to a bias transistor to Vcc and through a fuse device to a two transistor clamping circuit,   (c) the signal input to the output transistor and the first clamp transistors being a select signal,   (d) the second clamp transistor input being a memory RAS signal,   (e) the RAS and select signals in standby being in low voltage state and holding off the two clamp transistors and the select circuit output transistor,   (f) the gating transistor being biased on by the bias transistor connected to the gating transistor input,   (g) said output transistor being off and connected in series with said gating transistor preventing other than leakage current to flow through the gating transistor.   
     
     
       3. Multiple addressing paths of claim 1 wherein address paths for different addresses share same address path output circuitry to conserve on power as a result of only one repair address used at a time. 
     
     
       4. The address of the failing memory location of claim 1 comprising: (a) a logical one or a logical zero,   (b) said logical one caused by the propagation of an output signal of the select circuit through to the output of the address path,   (c) said logical zero caused by disconnecting the select circuit output signal from the address path by rendering a fuse device non-conductive and causing the signal output of the address path to be a result of Vcc connected through a bias transistor.   
     
     
       5. The address of the failing memory location of claim 4 wherein the select circuit output signal causes a logical zero at the address path output and the absence of the select circuit output signal causes a logical one at the address path output. 
     
     
       6. A select circuit having circuit means to provide low standby power and an output free of transient pulses and comprising: (a) an output transistor connected in series with a gating transistor,   (b) said gating transistor connected to circuit ground and the output transistor connected to Vcc through one or more bias transistors,   (c) the input to said output transistor being a section select signal,   (d) the input to said gating transistor being connected to two clamping transistors through a fuse device and to Vcc through a bias transistor,   (e) each of said two clamping transistors further connected to circuit ground and one being controlled on or off by said section select signal and the other by a memory RAS signal,   (f) said RAS signal preceding the section select signal, clamping off said gating transistor and preventing an error signal in the form of a transient pulse at the output of the select circuitry when said fuse device is conductive maintaining the connection of the clamp on the output circuitry,   (g) said section select signal maintaining the clamp signal on said gating transistor input until said section select signal is removed and output transistor is off,   (h) said fuse device when rendered non-conductive disconnecting clamping transistors from the circuit, allowing said gating transistor to be on and in turn allowing said output transistor to respond to section select signal.   
     
     
       7. The select circuit of claim 6 being connected to the memory RAS signal with other select circuits, (a) each select circuit having different select signals inputs,   (b) each select circuit output driving a different set of address paths.   
     
     
       8. The circuit of claim 6 wherein said circuit means to provide an output free of transient pulses comprising: (a) two clamp transistors connected in parallel between circuit ground and the input of the output gating transistor through a conductive fuse device,   (b) the output gating transistor connected between ground and the select circuit output transistor,   (c) a select signal connected to the output transistor and the first input of the clamp transistors,   (d) whereby when the select signal initially at low voltage holding said clamp transistor and said output transistor off with the gating transistor connected to the output transistor biased on,   (e) whereby when the select signal going high, turning on said clamp transistor and said output transistor, and turning off said gating transistor as a result of said clamp transistor turning on,   (f) the mismatch in delay between said output transistor turning on and the combination of said clamp transistor turning on and said gating transistor turning off producing the possibility of a transient pulse at the output,   (g) said transient pulse avoided by applying the memory RAS signal to the input to the second clamp transistor prior to the select signal and turning off the gating transistor before the output transistor is turned on.   
     
     
       9. A low power redundancy circuit for memory purposes providing addressing information for replacement of failing memory location and comprising: (a) multiple select circuits each containing a first fuse device and each connected to different sections of addressing circuitry,   (b) said first fuse when rendered non-conductive activating the select circuit and allowing selection of said addressing circuitry,   (c) said addressing circuitry consisting of multiple paths and each path of the addressing circuitry connected to an output of a select circuit,   (d) a second fuse device in each address path connected in series between the output of the select circuit and the input to the addressing circuitry,   (e) the connection between second fuse device and input to the addressing circuitry connected to Vcc through a bias transistor,   (f) said bias transistor providing bias to output of select circuit through said second fuse device,   (g) each said second fuse device when rendered conductive or non-conductive producing at the output of the paths of the addressing circuitry a signal with the value of a bit in the address of the failing memory location.   
     
     
       10. The circuit of claim 9 wherein said circuit for memory purposes providing addressing information for replacement of failing memory location and comprising: (a) several similar addressing paths connected to a select circuit output and each providing a logical bit of the address of the failing memory location,   (b) a fuse device in each addressing path connected in series between select circuit output and the junction between a bias transistor and an input to common circuitry shared with other addressing paths,   (c) the output signal of the select circuit providing a logical one signal at the output of the addressing paths when the fuse device is conductive,   (d) the fuse device when rendered non-conductive disconnecting the output of the select circuit from the addressing circuit and by absence of the select signal producing a logical zero at the output of the addressing paths.   
     
     
       11. The addressing path of claim 10 wherein the output of the select circuit signal produces a logical zero at the output of the addressing paths and the absence of the select circuit signal produces a logical one. 
     
     
       12. A clamp circuit controlling select circuit output off during and after a select signal transition comprising: (a) first and second clamp transistors connected in parallel between circuit ground and the input to a gating transistor through a fuse device,   (b) said gating transistor connected in series with an output transistor which in turn is connected to Vcc through a bias transistor at its output,   (c) signal input to said first clamp transistor being a memory RAS signal,   (d) signal input to said second clamp transistor and the output transistor being a select signal,   (e) the select and RAS signals being initially in a low voltage state controlling the clamp transistors off and the output transistor off and allowing the gating transistor to be biased on,   (f) the output of the output transistor being in a high voltage state,   (g) whereby when the RAS signal goes from a low voltage state to a high voltage state prior to the select signal going to a high voltage state controlling the gating transistor off,   (h) the output transistor turning on when the select signal goes to a high voltage,   (i) the output of the output transistor remaining high as a result of the gating transistor being held off by the RAS signal.   
     
     
       13. A select circuit comprising: (a) a transistor "nand" circuit with first input connected to the output of a transistor "nor" circuit and a bias transistor to Vcc,   (b) the output of said "nand" circuit being the select circuit output,   (c) said "nand" circuit and bias transistor separated from said "nor" circuit by a fuse device,   (d) a select signal connected to the second input of said "nand" circuit and the first input of said "nor" circuit,   (e) said "nor" circuit output controlling "nand" circuit off when select signal is present at the input of said "nor" circuit and fuse device in conductive,   (f) a memory RAS signal applied to the second input of the "nor" circuit in advance of the select signal to prevent a transient pulse at the output of the select circuit,   (g) the fuse device when rendered non-conductive disconnects the "nor" circuit output from the first input to the "nand" circuit and allowing said first input to the "nand" circuit to be biased on by the bias transistor,   (h) a select signal applied to the second input of the said "nand" circuit when the fuse device is rendered non-conductive produces a signal at the output of said "nand" circuit.   
     
     
       14. A low standby power memory circuit for selecting addressing information to replace failing memory locations, and comprising: (a) a low standby power select circuitry activated by rendering a first fuse device non-conductive,   (b) said select circuit, when activated, selecting a section of addressing paths through signal means,   (c) each addressing path having a second fuse device when conductive or non-conductive providing addressing information to replace failing memory locations,   (d) each address path grouped with other address paths into sections and each section providing the address of a different failing memory location,   (e) multiple sections of addressing paths, each activated and selected by a separate select circuit and sharing address path output circuitry with other sections,   (f) each section of address paths mutually exclusive of other sections of address paths with only one section being selected at a time,   (g) each section of addressing paths providing a different address for a different failing memory location.